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Update IPs based on up_adc_common changes

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AndreiGrozav 2023-01-12 11:10:23 +02:00 committed by Alin-Tudor Sferle
parent 8ad959c16f
commit 22fbb05256
15 changed files with 75 additions and 90 deletions
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11
library/axi_ad7768/axi_ad7768.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -311,11 +311,10 @@ module axi_ad7768 #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (NUM_CHANNELS),
.up_adc_gpio_in (32'b0),

11
library/axi_ad777x/axi_ad777x.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -307,11 +307,10 @@ module axi_ad777x #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8),
.up_adc_gpio_in (32'b0),

11
library/axi_ad9265/axi_ad9265.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -280,11 +280,10 @@ module axi_ad9265 #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd0),
.up_adc_gpio_in (32'd0),

11
library/axi_ad9361/axi_ad9361_rx.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -385,11 +385,10 @@ module axi_ad9361_rx #(
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd3),
.up_adc_gpio_in (up_adc_gpio_in),

11
library/axi_ad9434/axi_ad9434_core.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -202,11 +202,10 @@ module axi_ad9434_core #(
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),

11
library/axi_ad9467/axi_ad9467.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -271,11 +271,10 @@ module axi_ad9467#(
.up_drp_rdata (16'b0),
.up_drp_ready (1'b0),
.up_drp_locked (1'b1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd1),
.up_adc_gpio_in (32'd0),

11
library/axi_ad9625/axi_ad9625.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -235,11 +235,10 @@ module axi_ad9625 #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd1),
.up_adc_gpio_in (32'd0),

11
library/axi_ad9671/axi_ad9671.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -271,11 +271,10 @@ module axi_ad9671 #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd7),
.up_adc_gpio_in (32'd0),

11
library/axi_ad9684/axi_ad9684.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -259,11 +259,10 @@ module axi_ad9684 #(
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd1),
.up_adc_gpio_in (32'd0),

11
library/axi_ad9963/axi_ad9963_rx.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -263,11 +263,10 @@ module axi_ad9963_rx #(
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_in (8'd1),
.up_adc_gpio_in (32'h0),
.up_adc_gpio_out (),

11
library/axi_adaq8092/axi_adaq8092.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -333,11 +333,10 @@ module axi_adaq8092 #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd0),
.up_adc_gpio_in (32'd0),

11
library/axi_adrv9001/axi_adrv9001_rx.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -390,11 +390,10 @@ module axi_adrv9001_rx #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd3),
.up_adc_gpio_in (32'd0),

11
library/axi_generic_adc/axi_generic_adc.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -158,11 +158,10 @@ module axi_generic_adc #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (NUM_OF_CHANNELS),
.up_adc_gpio_in (32'b0),

11
library/axi_ltc2387/axi_ltc2387.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2021 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -287,11 +287,10 @@ module axi_ltc2387 #(
.up_drp_rdata (32'b0),
.up_drp_ready (1'b0),
.up_drp_locked (1'b1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd1),
.up_adc_gpio_in (32'd0),

11
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2018-2023 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
@ -242,11 +242,10 @@ module ad_ip_jesd204_tpl_adc_regmap #(
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_custom_wr (),
.adc_write_req (),
.adc_custom_rd ('d0),
.adc_read_valid ('d0),
.adc_read_req (),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (NUM_CHANNELS),
.up_adc_gpio_in (32'd0),