Remove library/scripts/common_bd.tcl
Remove the script from the file list of the IPs that previously used it. axi_clkgen: Add independent adi_auto_assign_device_spec procmain
parent
7dcaaea04e
commit
23841478c6
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@ -9,13 +9,12 @@ adi_ip_files axi_clkgen [list \
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"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
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"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_clkgen.v" \
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"$ad_hdl_dir/library/common/up_clkgen.v" \
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"$ad_hdl_dir/library/scripts/common_bd.tcl" \
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"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
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"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
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"bd/bd.tcl" \
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"bd/bd.tcl" \
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"axi_clkgen.v" ]
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"axi_clkgen.v" ]
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adi_ip_properties axi_clkgen
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adi_ip_properties axi_clkgen
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adi_ip_bd axi_clkgen "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl"
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adi_ip_bd axi_clkgen "bd/bd.tcl"
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ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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@ -48,9 +48,6 @@ proc init {cellpath otherInfo} {
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DEV_PACKAGE \
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DEV_PACKAGE \
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FPGA_VOLTAGE"
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FPGA_VOLTAGE"
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set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
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source ${ip_path}../scripts/common_bd.tcl
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adi_auto_assign_device_spec $cellpath
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adi_auto_assign_device_spec $cellpath
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}
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}
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@ -69,6 +66,39 @@ proc axi_clkgen_get_infer_period {ip param clk_name} {
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}
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}
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}
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}
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proc adi_auto_assign_device_spec {cellpath} {
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set ip [get_bd_cells $cellpath]
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set ip_param_list [list_property $ip]
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set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
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set parent_dir "../"
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for {set x 1} {$x<=4} {incr x} {
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set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
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if { [file exists $linkname] } {
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source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
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break
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}
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append parent_dir "../"
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}
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# Find predefindes auto assignable parameters
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foreach i $auto_set_param_list {
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if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
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set val [adi_device_spec $cellpath $i]
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set_property CONFIG.$i $val $ip
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}
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}
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# Find predefindes auto assignable/overwritable parameters
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foreach i $auto_set_param_list_overwritable {
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if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
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set val [adi_device_spec $cellpath $i]
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set_property CONFIG.$i $val $ip
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}
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}
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}
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proc propagate {cellpath otherinfo} {
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proc propagate {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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set ip [get_bd_cells $cellpath]
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@ -1,61 +0,0 @@
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## ***************************************************************************
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## ***************************************************************************
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## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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##
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## In this HDL repository, there are many different and unique modules, consisting
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## of various HDL (Verilog or VHDL) components. The individual modules are
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## developed independently, and may be accompanied by separate and unique license
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## terms.
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##
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## The user should read each of these license terms, and understand the
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## freedoms and responsibilities that he or she has by using this source/core.
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##
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## This core is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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## A PARTICULAR PURPOSE.
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##
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## Redistribution and use of source or resulting binaries, with or without modification
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## of this file, are permitted under one of the following two license terms:
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##
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## 1. The GNU General Public License version 2 as published by the
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## Free Software Foundation, which can be found in the top level directory
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## of this repository (LICENSE_GPL2), and also online at:
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## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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##
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## OR
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##
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## 2. An ADI specific BSD license, which can be found in the top level directory
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## of this repository (LICENSE_ADIBSD), and also on-line at:
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## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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## This will allow to generate bit files and not release the source code,
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## as long as it attaches to an ADI device.
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##
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## ***************************************************************************
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## ***************************************************************************
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# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
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proc adi_auto_assign_device_spec {cellpath} {
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set ip [get_bd_cells $cellpath]
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set ip_param_list [list_property $ip]
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set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
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set parent_dir "../"
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for {set x 1} {$x<=4} {incr x} {
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set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
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if { [file exists $linkname] } {
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source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
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break
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}
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append parent_dir "../"
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}
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# Find predefindes auto assignable parameters
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foreach i $auto_set_param_list {
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if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
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set val [adi_device_spec $cellpath $i]
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set_property CONFIG.$i $val $ip
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}
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}
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}
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@ -6,7 +6,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_adxcvr
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adi_ip_create axi_adxcvr
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adi_ip_files axi_adxcvr [list \
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adi_ip_files axi_adxcvr [list \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/scripts/common_bd.tcl" \
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"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
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"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
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"axi_adxcvr_es.v" \
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"axi_adxcvr_es.v" \
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"axi_adxcvr_up.v" \
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"axi_adxcvr_up.v" \
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@ -5,7 +5,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create util_adxcvr
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adi_ip_create util_adxcvr
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adi_ip_files util_adxcvr [list \
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adi_ip_files util_adxcvr [list \
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"$ad_hdl_dir/library/scripts/common_bd.tcl" \
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"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
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"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
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"util_adxcvr_constr.xdc" \
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"util_adxcvr_constr.xdc" \
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"util_adxcvr_xcm.v" \
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"util_adxcvr_xcm.v" \
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