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axi_dmac: Add transfer testbenches 

Add simple transfer testbenches that test the read and write to AXI memory
paths of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-09-07 14:56:33 +02:00 committed by Lars-Peter Clausen
parent b3f027fc89
commit 24d17e8bcc
7 changed files with 667 additions and 0 deletions
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97
library/axi_dmac/tb/axi_read_slave.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
module axi_read_slave #(
parameter DATA_WIDTH = 32,
parameter READ_ACCEPTANCE = 4,
parameter MIN_LATENCY = 48,
parameter MAX_LATENCY = 48
) (
input clk,
input reset,
input arvalid,
output arready,
input [31:0] araddr,
input [7:0] arlen,
input [2:0] arsize,
input [1:0] arburst,
input [2:0] arprot,
input [3:0] arcache,
output rvalid,
input rready,
output [DATA_WIDTH-1:0] rdata,
output [1:0] rresp,
output rlast
);
reg [DATA_WIDTH-1:0] data = 'h00;
assign rresp = 2'b00;
//assign rdata = data;
always @(posedge clk) begin
if (reset == 1'b1) begin
data <= 'h00;
end else if (rvalid == 1'b1 && rready == 1'b1) begin
data <= data + 1'b1;
end
end
axi_slave #(
.ACCEPTANCE(READ_ACCEPTANCE),
.MIN_LATENCY(MIN_LATENCY),
.MAX_LATENCY(MAX_LATENCY)
) i_axi_slave (
.clk(clk),
.reset(reset),
.valid(arvalid),
.ready(arready),
.addr(araddr),
.len(arlen),
.size(arsize),
.burst(arburst),
.prot(arprot),
.cache(arcache),
.beat_stb(rvalid),
.beat_ack(rvalid & rready),
.beat_last(rlast),
.beat_addr(rdata)
);
endmodule

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library/axi_dmac/tb/axi_slave.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
module axi_slave #(
parameter ACCEPTANCE = 3,
parameter MIN_LATENCY = 16,
parameter MAX_LATENCY = 32
) (
input clk,
input reset,
input valid,
output ready,
input [31:0] addr,
input [7:0] len,
input [2:0] size,
input [1:0] burst,
input [2:0] prot,
input [3:0] cache,
output beat_stb,
input beat_ack,
output [31:0] beat_addr,
output beat_last
);
reg [31:0] timestamp = 'h00;
always @(posedge clk) begin
if (reset == 1'b1) begin
timestamp <= 'h00;
end else begin
timestamp <= timestamp + 1'b1;
end
end
reg [32+32+8-1:0] req_fifo[0:15];
reg [3:0] req_fifo_rd = 'h00;
reg [3:0] req_fifo_wr = 'h00;
wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;
assign ready = req_fifo_level < ACCEPTANCE;
always @(posedge clk) begin
if (reset == 1'b1) begin
req_fifo_wr <= 'h00;
end else begin
if (valid == 1'b1 && ready == 1'b1) begin
req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY;
req_fifo[req_fifo_wr][39:0] <= {addr,len};
req_fifo_wr <= req_fifo_wr + 1'b1;
end
end
end
reg [7:0] beat_counter = 'h00;
assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40];
assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0;
assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * 4;
always @(posedge clk) begin
if (reset == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= 'h00;
end else begin
if (beat_ack == 1'b1) begin
if (beat_last == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= req_fifo_rd + 1'b1;
end else begin
beat_counter <= beat_counter + 1'b1;
end
end
end
end
endmodule

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library/axi_dmac/tb/axi_write_slave.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
module axi_write_slave #(
parameter DATA_WIDTH = 32,
parameter WRITE_ACCEPTANCE = 3
) (
input clk,
input reset,
input awvalid,
output awready,
input [31:0] awaddr,
input [7:0] awlen,
input [2:0] awsize,
input [1:0] awburst,
input [2:0] awprot,
input [3:0] awcache,
input wvalid,
output wready,
input [DATA_WIDTH-1:0] wdata,
input [DATA_WIDTH/8-1:0] wstrb,
input wlast,
output reg bvalid,
input bready,
output [1:0] bresp
);
wire beat_last;
axi_slave #(
.ACCEPTANCE(WRITE_ACCEPTANCE)
) i_axi_slave (
.clk(clk),
.reset(reset),
.valid(awvalid),
.ready(awready),
.addr(awaddr),
.len(awlen),
.size(awsize),
.burst(awburst),
.prot(awprot),
.cache(awcache),
.beat_stb(wready),
.beat_ack(wvalid & wready),
.beat_last(beat_last)
);
reg [4:0] resp_count = 'h00;
wire [4:0] resp_count_next;
assign bresp = 2'b00;
wire resp_count_dec = bvalid & bready == 1'b1 ? 1'b1 : 1'b0;
wire resp_count_inc = wvalid == 1'b1 && wready == 1'b1 && beat_last == 1'b1 ? 1'b1 : 1'b0;
assign resp_count_next = resp_count - resp_count_dec + resp_count_inc;
always @(posedge clk) begin
if (reset == 1'b1) begin
resp_count <= 'h00;
end else begin
resp_count <= resp_count - resp_count_dec + resp_count_inc;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
bvalid <= 1'b0;
end else if (bvalid == 1'b0 || bready == 1'b1) begin
if (resp_count_next != 'h00) begin
bvalid <= {$random} % 4 == 0;
end else begin
bvalid <= 1'b0;
end
end
end
endmodule

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#!/bin/bash
SOURCE="dma_read_tb.v"
SOURCE+=" axi_read_slave.v axi_slave.v"
SOURCE+=" ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../data_mover.v ../axi_register_slice.v"
SOURCE+=" ../dest_fifo_inf.v"
SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v ../../util_axis_fifo/address_gray_pipelined.v"
SOURCE+=" ../../common/ad_mem.v"
SOURCE+=" ../../util_cdc/sync_bits.v ../../util_cdc/sync_gray.v"
SOURCE+=" ../../util_axis_resize/util_axis_resize.v"
cd `dirname $0`
source run_tb.sh

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library/axi_dmac/tb/dma_read_tb.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_dma_read_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`include "tb_base.v"
localparam TRANSFER_ADDR = 32'h80000000;
localparam TRANSFER_LEN = 24'h203;
reg req_valid = 1'b1;
wire req_ready;
reg [23:0] req_length = 'h03;
wire awvalid;
wire awready;
wire [31:0] araddr;
wire [7:0] arlen;
wire [2:0] arsize;
wire [1:0] arburst;
wire [2:0] arprot;
wire [3:0] arcache;
wire rlast;
wire rvalid;
wire rready;
wire [1:0] rresp;
wire [31:0] rdata;
always @(posedge clk) begin
if (reset != 1'b1 && req_ready == 1'b1) begin
req_valid <= 1'b1;
req_length <= req_length + 4;
end
end
axi_read_slave #(
.DATA_WIDTH(32)
) i_write_slave (
.clk(clk),
.reset(reset),
.arvalid(arvalid),
.arready(arready),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arprot(arprot),
.arcache(arcache),
.rready(rready),
.rvalid(rvalid),
.rdata(rdata),
.rresp(rresp),
.rlast(rlast)
);
wire fifo_rd_en = 1'b1;
wire fifo_rd_valid;
wire fifo_rd_underflow;
wire [31:0] fifo_rd_dout;
reg [31:0] fifo_rd_dout_cmp = TRANSFER_ADDR;
reg fifo_rd_dout_mismatch = 1'b0;
reg [31:0] fifo_rd_dout_limit = 'h0;
dmac_request_arb #(
.DMA_TYPE_SRC(0),
.DMA_TYPE_DEST(2),
.DMA_DATA_WIDTH_SRC(32),
.DMA_DATA_WIDTH_DEST(32),
.FIFO_SIZE(8)
) request_arb (
.m_src_axi_aclk (clk),
.m_src_axi_aresetn(resetn),
.m_axi_arvalid(arvalid),
.m_axi_arready(arready),
.m_axi_araddr(araddr),
.m_axi_arlen(arlen),
.m_axi_arsize(arsize),
.m_axi_arburst(arburst),
.m_axi_arprot(arprot),
.m_axi_arcache(arcache),
.m_axi_rready(rready),
.m_axi_rvalid(rvalid),
.m_axi_rdata(rdata),
.m_axi_rresp(rresp),
.req_aclk(clk),
.req_aresetn(resetn),
.enable(1'b1),
.pause(1'b0),
.eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_dest_address(TRANSFER_ADDR[31:2]),
.req_src_address(TRANSFER_ADDR[31:2]),
.req_length(req_length),
.req_sync_transfer_start(1'b0),
.fifo_rd_clk(clk),
.fifo_rd_en(fifo_rd_en),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_underflow(fifo_rd_underflow),
.fifo_rd_dout(fifo_rd_dout)
);
always @(posedge clk) begin
if (reset == 1'b1) begin
fifo_rd_dout_cmp <= TRANSFER_ADDR;
fifo_rd_dout_mismatch <= 1'b0;
end else begin
fifo_rd_dout_mismatch <= 1'b0;
if (fifo_rd_valid == 1'b1) begin
if (fifo_rd_dout_cmp < TRANSFER_ADDR + fifo_rd_dout_limit) begin
fifo_rd_dout_cmp <= (fifo_rd_dout_cmp + 'h4);
end else begin
fifo_rd_dout_cmp <= TRANSFER_ADDR;
fifo_rd_dout_limit <= fifo_rd_dout_limit + 'h4;
end
if (fifo_rd_dout_cmp != fifo_rd_dout) begin
fifo_rd_dout_mismatch <= 1'b1;
end
end
end
end
always @(posedge clk) begin
failed <= failed | fifo_rd_dout_mismatch;
end
endmodule

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library/axi_dmac/tb/dma_write_tb Executable file
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#!/bin/bash
SOURCE="dma_write_tb.v"
SOURCE+=" axi_write_slave.v axi_slave.v"
SOURCE+=" ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../data_mover.v ../axi_register_slice.v"
SOURCE+=" ../src_fifo_inf.v"
SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v ../../util_axis_fifo/address_gray_pipelined.v"
SOURCE+=" ../../common/ad_mem.v"
SOURCE+=" ../../util_cdc/sync_bits.v ../../util_cdc/sync_gray.v"
SOURCE+=" ../../util_axis_resize/util_axis_resize.v"
cd `dirname $0`
source run_tb.sh

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library/axi_dmac/tb/dma_write_tb.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_dma_write_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`include "tb_base.v"
reg req_valid = 1'b1;
wire req_ready;
wire awvalid;
wire awready;
wire [31:0] awaddr;
wire [7:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
wire [2:0] awprot;
wire [3:0] awcache;
wire wlast;
wire wvalid;
wire wready;
wire [3:0] wstrb;
wire [31:0] wdata;
wire bready;
wire bvalid;
wire [1:0] bresp;
always @(posedge clk) begin
if (reset != 1'b1 && req_ready == 1'b1) begin
req_valid <= 1'b1;
end
end
axi_write_slave #(
.DATA_WIDTH(32)
) i_write_slave (
.clk(clk),
.reset(reset),
.awvalid(awvalid),
.awready(awready),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awprot(awprot),
.awcache(awcache),
.wready(wready),
.wvalid(wvalid),
.wdata(wdata),
.wstrb(wstrb),
.wlast(wlast),
.bvalid(bvalid),
.bready(bready),
.bresp(bresp)
);
dmac_request_arb #(
.DMA_DATA_WIDTH_SRC(32),
.DMA_DATA_WIDTH_DEST(32)
) request_arb (
.m_dest_axi_aclk (clk),
.m_dest_axi_aresetn(resetn),
.m_axi_awvalid(awvalid),
.m_axi_awready(awready),
.m_axi_awaddr(awaddr),
.m_axi_awlen(awlen),
.m_axi_awsize(awsize),
.m_axi_awburst(awburst),
.m_axi_awprot(awprot),
.m_axi_awcache(awcache),
.m_axi_wready(wready),
.m_axi_wvalid(wvalid),
.m_axi_wdata(wdata),
.m_axi_wstrb(wstrb),
.m_axi_wlast(wlast),
.m_axi_bvalid(bvalid),
.m_axi_bready(bready),
.m_axi_bresp(bresp),
.req_aclk(clk),
.req_aresetn(resetn),
.enable(1'b1),
.pause(1'b0),
.eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_dest_address(30'h7e09000),
.req_length(24'h1ff),
.req_sync_transfer_start(1'b0),
.fifo_wr_clk(clk),
.fifo_wr_en(1'b1),
.fifo_wr_din(32'h00),
.fifo_wr_sync(1'b1),
.fifo_wr_xfer_req()
);
endmodule