diff --git a/projects/pmods/ad7175_zed/system_bd.tcl b/projects/pmods/ad7175_zed/system_bd.tcl new file mode 100644 index 000000000..082a9e99a --- /dev/null +++ b/projects/pmods/ad7175_zed/system_bd.tcl @@ -0,0 +1,91 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7 +set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect +set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc + +set_property LEFT 31 [get_bd_ports GPIO_I] +set_property LEFT 31 [get_bd_ports GPIO_O] +set_property LEFT 31 [get_bd_ports GPIO_T] + +set adc_sdo_i [create_bd_port -dir I adc_sdo_i] +set adc_sdi_o [create_bd_port -dir O adc_sdi_o] +set adc_cs_o [create_bd_port -dir O adc_cs_o] +set adc_sclk_o [create_bd_port -dir O adc_sclk_o] +set dma_data [create_bd_port -dir I -from 63 -to 0 dma_data] +set adc_data_0 [create_bd_port -dir O -from 31 -to 0 adc_data_0] +set adc_data_1 [create_bd_port -dir O -from 31 -to 0 adc_data_1] + +set axi_ad7175 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad7175:1.0 axi_ad7175] + +set axi_ad7175_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad7175_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad7175_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad7175_dma + +set axi_ad7175_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad7175_dma_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad7175_dma_interconnect + +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {10.0}] $sys_ps7 + +set sys_adc_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] + +connect_bd_net -net axi_ad7175_adc_sdo_i [get_bd_ports adc_sdo_i] [get_bd_pins axi_ad7175/adc_sdo_i] +connect_bd_net -net axi_ad7175_adc_sdi_o [get_bd_ports adc_sdi_o] [get_bd_pins axi_ad7175/adc_sdi_o] +connect_bd_net -net axi_ad7175_adc_cs_o [get_bd_ports adc_cs_o] [get_bd_pins axi_ad7175/adc_cs_o] +connect_bd_net -net axi_ad7175_adc_sclk_o [get_bd_ports adc_sclk_o] [get_bd_pins axi_ad7175/adc_sclk_o] + +connect_bd_net -net axi_ad7175_dma_valid [get_bd_pins axi_ad7175/adc_valid_1] [get_bd_pins axi_ad7175_dma/fifo_wr_en] + +connect_bd_net -net axi_ad7175_dma_data_0 [get_bd_pins axi_ad7175/adc_data_0] [get_bd_ports adc_data_0] +connect_bd_net -net axi_ad7175_dma_data_1 [get_bd_pins axi_ad7175/adc_data_1] [get_bd_ports adc_data_1] +connect_bd_net -net axi_ad7175_dma_data [get_bd_ports dma_data] [get_bd_pins axi_ad7175_dma/fifo_wr_din] + +connect_bd_net -net axi_ad7175_dma_dovf [get_bd_pins axi_ad7175/adc_dovf] [get_bd_pins axi_ad7175_dma/fifo_wr_overflow] + +connect_bd_net -net sys_adc_clk_source [get_bd_pins axi_ad7175/adc_clk_i] $sys_adc_clk_source +connect_bd_net -net sys_adc_dma_clk [get_bd_pins axi_ad7175_dma/fifo_wr_clk] [get_bd_pins axi_ad7175/adc_clk] + +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad7175/s_axi_aclk] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad7175_dma/s_axi_aclk] $sys_100m_clk_source + +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175/s_axi_aresetn] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma/s_axi_aresetn] $sys_100m_resetn_source + +connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad7175_dma/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad7175/s_axi] + +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + +connect_bd_intf_net -intf_net axi_ad7175_dma_interconnect_s0 [get_bd_intf_pins axi_ad7175_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad7175_dma/m_dest_axi] +connect_bd_intf_net -intf_net axi_ad7175_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad7175_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + +connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad7175_dma_interconnect/S00_ACLK] $sys_200m_clk_source +connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad7175_dma/m_dest_axi_aclk] +connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] +connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad7175_dma_interconnect/ACLK] $sys_200m_clk_source +connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad7175_dma_interconnect/M00_ACLK] $sys_200m_clk_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source + +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma/m_dest_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad7175_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source + +create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad7175/s_axi/axi_lite] SEG_data_ad7175_core +create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad7175_dma/s_axi/axi_lite] SEG_data_ad7175_dma + +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad7175_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm \ No newline at end of file diff --git a/projects/pmods/ad7175_zed/system_constr.xdc b/projects/pmods/ad7175_zed/system_constr.xdc new file mode 100644 index 000000000..5b1c4beb8 --- /dev/null +++ b/projects/pmods/ad7175_zed/system_constr.xdc @@ -0,0 +1,11 @@ + +# PMOD JA + +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports adc_cs_o]; +set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports adc_sdi_o]; +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports adc_sdo_i]; +set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports adc_sclk_o]; +#set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS33} [get_ports gain_o]; +#set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS33} [get_ports led_clk_o]; +#set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports ad_sync_nc]; +#set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ad_clkio_nc]; \ No newline at end of file diff --git a/projects/pmods/ad7175_zed/system_project.tcl b/projects/pmods/ad7175_zed/system_project.tcl new file mode 100644 index 000000000..a4def392d --- /dev/null +++ b/projects/pmods/ad7175_zed/system_project.tcl @@ -0,0 +1,15 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create adv7511_zed +adi_project_files adv7511_zed [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] + +adi_project_run adv7511_zed + + diff --git a/projects/pmods/ad7175_zed/system_top.v b/projects/pmods/ad7175_zed/system_top.v new file mode 100644 index 000000000..ed4ecb196 --- /dev/null +++ b/projects/pmods/ad7175_zed/system_top.v @@ -0,0 +1,236 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + spdif, + + iic_scl, + iic_sda, + iic_mux_scl, + iic_mux_sda, + + adc_sdo_i, + adc_sdi_o, + adc_cs_o, + adc_sclk_o, + + otg_vbusoc); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [31:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + + inout iic_scl; + inout iic_sda; + inout [ 1:0] iic_mux_scl; + inout [ 1:0] iic_mux_sda; + + input adc_sdo_i; + output adc_sdi_o; + output adc_cs_o; + output adc_sclk_o; + + input otg_vbusoc; + + // internal signals + + wire [31:0] gpio_i; + wire [31:0] gpio_o; + wire [31:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire [31:0] adc_data_0; + wire [31:0] adc_data_1; + wire [63:0] dma_data; + + // instantiations + + genvar n; + generate + for (n = 0; n <= 31; n = n + 1) begin: g_iobuf_gpio_bd + IOBUF i_iobuf_gpio_bd ( + .I (gpio_o[n]), + .O (gpio_i[n]), + .T (gpio_t[n]), + .IO (gpio_bd[n])); + end + endgenerate + + IOBUF i_iic_mux_scl_0 (.I(iic_mux_scl_o_s[0]), .O(iic_mux_scl_i_s[0]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[0])); + IOBUF i_iic_mux_scl_1 (.I(iic_mux_scl_o_s[1]), .O(iic_mux_scl_i_s[1]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[1])); + IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0])); + IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1])); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_I (iic_mux_scl_i_s), + .iic_mux_scl_O (iic_mux_scl_o_s), + .iic_mux_scl_T (iic_mux_scl_t_s), + .iic_mux_sda_I (iic_mux_sda_i_s), + .iic_mux_sda_O (iic_mux_sda_o_s), + .iic_mux_sda_T (iic_mux_sda_t_s), + .adc_sdo_i (adc_sdo_i), + .adc_sdi_o (adc_sdi_o), + .adc_cs_o (adc_cs_o), + .adc_sclk_o (adc_sclk_o), + .dma_data ({adc_data_1, adc_data_0}), + .adc_data_1(adc_data_1), + .adc_data_0(adc_data_0), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// ***************************************************************************