zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

library/xilinx/util_adxcvr: merge GTY and GTH prefixed parameter 

parameters with same names were duplicated with transceiver specific
names due different default values.
This does not scales very well.

Use same name for the parameters as for other parameters and do the
default value handling in the IP configuration layer.
main
Laszlo Nagy 2019-11-14 13:22:09 +00:00 committed by Laszlo Nagy
parent 9cce513645
commit 253b1149ad
6 changed files with 179 additions and 166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
library/xilinx/util_adxcvr/Makefile
View File

@ -15,6 +15,7 @@ XILINX_DEPS += ../../interfaces/if_xcvr_ch.xml
XILINX_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
XILINX_DEPS += ../../interfaces/if_xcvr_cm.xml
XILINX_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
XILINX_DEPS += bd/bd.tcl
XILINX_INTERFACE_DEPS += interfaces

44
library/xilinx/util_adxcvr/bd/bd.tcl Normal file
View File

@ -0,0 +1,44 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_override $ip " \
XCVR_TYPE CH_HSPMUX PPF0_CFG RXPI_CFG0 RXPI_CFG1 RTX_BUF_CML_CTRL"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}

234
library/xilinx/util_adxcvr/util_adxcvr.v
View File

@ -60,7 +60,6 @@ module util_adxcvr #(
parameter [15:0] QPLL_CP_G3 = 10'b0000011111,
parameter [15:0] QPLL_LPF = 10'b0100110111,
parameter [15:0] QPLL_CP = 10'b0001111111,
parameter [15:0] GTY4_PPF0_CFG = 16'b0000100000000000,
// cpll-configuration
@ -70,14 +69,11 @@ module util_adxcvr #(
parameter [15:0] CPLL_CFG1 = 16'b0000000000100011,
parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,
parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,
parameter [15:0] GTH4_CH_HSPMUX = 16'b0010010000100100,
parameter integer GTH4_PREIQ_FREQ_BST = 0,
parameter [15:0] GTH4_RXPI_CFG0 = 16'b0000000000000010,
parameter [15:0] GTH4_RXPI_CFG1 = 16'b0000000000010101,
parameter [15:0] GTY4_CH_HSPMUX = 16'b0010000000100000,
parameter integer GTY4_PREIQ_FREQ_BST = 0,
parameter [2:0] GTY4_RTX_BUF_CML_CTRL = 3'b011,
parameter [15:0] GTY4_RXPI_CFG0 = 16'b0000000100000000,
parameter [15:0] CH_HSPMUX = 16'b0010010000100100,
parameter integer PREIQ_FREQ_BST = 0,
parameter [15:0] RXPI_CFG0 = 16'b0000000000000010,
parameter [15:0] RXPI_CFG1 = 16'b0000000000010101,
parameter [2:0] RTX_BUF_CML_CTRL = 3'b011,
// tx-configuration
@ -1159,8 +1155,7 @@ module util_adxcvr #(
.QPLL_CP_G3 (QPLL_CP_G3),
.QPLL_LPF (QPLL_LPF),
.QPLL_CP (QPLL_CP),
.QPLL_CFG4 (QPLL_CFG4),
.GTY4_PPF0_CFG (GTY4_PPF0_CFG))
.QPLL_CFG4 (QPLL_CFG4))
i_xcm_0 (
.qpll_ref_clk (qpll_ref_clk_0),
.qpll_sel (qpll_sel_0),
@ -1220,14 +1215,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_0 (
.qpll2ch_clk (qpll2ch_clk_0),
.qpll2ch_ref_clk (qpll2ch_ref_clk_0),
@ -1344,14 +1336,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_1 (
.qpll2ch_clk (qpll2ch_clk_0),
.qpll2ch_ref_clk (qpll2ch_ref_clk_0),
@ -1468,14 +1457,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_2 (
.qpll2ch_clk (qpll2ch_clk_0),
.qpll2ch_ref_clk (qpll2ch_ref_clk_0),
@ -1592,14 +1578,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_3 (
.qpll2ch_clk (qpll2ch_clk_0),
.qpll2ch_ref_clk (qpll2ch_ref_clk_0),
@ -1705,8 +1688,7 @@ module util_adxcvr #(
.QPLL_CP_G3 (QPLL_CP_G3),
.QPLL_LPF (QPLL_LPF),
.QPLL_CP (QPLL_CP),
.QPLL_CFG4 (QPLL_CFG4),
.GTY4_PPF0_CFG (GTY4_PPF0_CFG))
.QPLL_CFG4 (QPLL_CFG4))
i_xcm_4 (
.qpll_ref_clk (qpll_ref_clk_4),
.qpll_sel (qpll_sel_4),
@ -1766,14 +1748,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_4 (
.qpll2ch_clk (qpll2ch_clk_4),
.qpll2ch_ref_clk (qpll2ch_ref_clk_4),
@ -1890,14 +1869,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_5 (
.qpll2ch_clk (qpll2ch_clk_4),
.qpll2ch_ref_clk (qpll2ch_ref_clk_4),
@ -2014,14 +1990,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_6 (
.qpll2ch_clk (qpll2ch_clk_4),
.qpll2ch_ref_clk (qpll2ch_ref_clk_4),
@ -2138,14 +2111,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_7 (
.qpll2ch_clk (qpll2ch_clk_4),
.qpll2ch_ref_clk (qpll2ch_ref_clk_4),
@ -2251,8 +2221,7 @@ module util_adxcvr #(
.QPLL_CP_G3 (QPLL_CP_G3),
.QPLL_LPF (QPLL_LPF),
.QPLL_CP (QPLL_CP),
.QPLL_CFG4 (QPLL_CFG4),
.GTY4_PPF0_CFG (GTY4_PPF0_CFG))
.QPLL_CFG4 (QPLL_CFG4))
i_xcm_8 (
.qpll_ref_clk (qpll_ref_clk_8),
.qpll_sel (qpll_sel_8),
@ -2312,14 +2281,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_8 (
.qpll2ch_clk (qpll2ch_clk_8),
.qpll2ch_ref_clk (qpll2ch_ref_clk_8),
@ -2436,14 +2402,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_9 (
.qpll2ch_clk (qpll2ch_clk_8),
.qpll2ch_ref_clk (qpll2ch_ref_clk_8),
@ -2560,14 +2523,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_10 (
.qpll2ch_clk (qpll2ch_clk_8),
.qpll2ch_ref_clk (qpll2ch_ref_clk_8),
@ -2684,14 +2644,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_11 (
.qpll2ch_clk (qpll2ch_clk_8),
.qpll2ch_ref_clk (qpll2ch_ref_clk_8),
@ -2797,8 +2754,7 @@ module util_adxcvr #(
.QPLL_CP_G3 (QPLL_CP_G3),
.QPLL_LPF (QPLL_LPF),
.QPLL_CP (QPLL_CP),
.QPLL_CFG4 (QPLL_CFG4),
.GTY4_PPF0_CFG (GTY4_PPF0_CFG))
.QPLL_CFG4 (QPLL_CFG4))
i_xcm_12 (
.qpll_ref_clk (qpll_ref_clk_12),
.qpll_sel (qpll_sel_12),
@ -2858,14 +2814,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_12 (
.qpll2ch_clk (qpll2ch_clk_12),
.qpll2ch_ref_clk (qpll2ch_ref_clk_12),
@ -2982,14 +2935,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_13 (
.qpll2ch_clk (qpll2ch_clk_12),
.qpll2ch_ref_clk (qpll2ch_ref_clk_12),
@ -3106,14 +3056,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_14 (
.qpll2ch_clk (qpll2ch_clk_12),
.qpll2ch_ref_clk (qpll2ch_ref_clk_12),
@ -3230,14 +3177,11 @@ module util_adxcvr #(
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0))
.CH_HSPMUX (CH_HSPMUX),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL))
i_xch_15 (
.qpll2ch_clk (qpll2ch_clk_12),
.qpll2ch_ref_clk (qpll2ch_ref_clk_12),

32
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
View File

@ -9,11 +9,11 @@ adi_ip_files util_adxcvr [list \
"util_adxcvr_constr.xdc" \
"util_adxcvr_xcm.v" \
"util_adxcvr_xch.v" \
"util_adxcvr.v" ]
"util_adxcvr.v" \
"bd/bd.tcl" ]
adi_ip_properties_lite util_adxcvr
adi_init_bd_tcl
adi_ip_bd util_adxcvr "bd/bd.tcl"
ipx::remove_all_bus_interface [ipx::current_core]
@ -810,6 +810,34 @@ set_property enablement_dependency \
[ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]]
adi_add_auto_fpga_spec_params
set cc [ipx::current_core]
set param [ipx::get_user_parameters CH_HSPMUX -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : \
{$XCVR_TYPE == 9} ? 0x2020 : 0x0]]} \
] $param
set param [ipx::get_user_parameters PPF0_CFG -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]} \
] $param
set param [ipx::get_user_parameters RXPI_CFG0 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : \
{$XCVR_TYPE == 9} ? 0x100 : 0x0]]} \
] $param
set param [ipx::get_user_parameters RXPI_CFG1 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]} \
] $param
set param [ipx::get_user_parameters RTX_BUF_CML_CTRL -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]} \
] $param
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]

29
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -48,15 +48,12 @@ module util_adxcvr_xch #(
parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,
parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,
parameter [15:0] GTH4_CH_HSPMUX = 16'b0010010000100100,
parameter integer GTH4_PREIQ_FREQ_BST = 0,
parameter [15:0] GTH4_RXPI_CFG0 = 16'b0000000000000010,
parameter [15:0] GTH4_RXPI_CFG1 = 16'b0000000000010101,
parameter [15:0] CH_HSPMUX = 16'b0010010000100100,
parameter integer PREIQ_FREQ_BST = 0,
parameter [15:0] RXPI_CFG0 = 16'b0000000000000010,
parameter [15:0] RXPI_CFG1 = 16'b0000000000010101,
parameter [15:0] GTY4_CH_HSPMUX = 16'b0010000000100000,
parameter integer GTY4_PREIQ_FREQ_BST = 0,
parameter [2:0] GTY4_RTX_BUF_CML_CTRL = 3'b011,
parameter [15:0] GTY4_RXPI_CFG0 = 16'b0000000100000000,
parameter [2:0] RTX_BUF_CML_CTRL = 3'b011,
parameter integer TX_OUT_DIV = 1,
parameter integer TX_CLK25_DIV = 20,
@ -1600,7 +1597,7 @@ module util_adxcvr_xch #(
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.CH_HSPMUX (GTH4_CH_HSPMUX),
.CH_HSPMUX (CH_HSPMUX),
.CKCAL1_CFG_0 (16'b1100000011000000),
.CKCAL1_CFG_1 (16'b0101000011000000),
.CKCAL1_CFG_2 (16'b0000000000001010),
@ -1728,7 +1725,7 @@ module util_adxcvr_xch #(
.PD_TRANS_TIME_FROM_P2 (12'b000000111100),
.PD_TRANS_TIME_NONE_P2 (8'b00011001),
.PD_TRANS_TIME_TO_P2 (8'b01100100),
.PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.PROCESS_PAR (3'b010),
.RATE_SW_USE_DRP (1'b1),
.RCLK_SIPO_DLY_ENB (1'b0),
@ -1856,8 +1853,8 @@ module util_adxcvr_xch #(
.RXPHSLIP_CFG (16'b1001100100110011),
.RXPH_MONITOR_SEL (5'b00000),
.RXPI_AUTO_BW_SEL_BYPASS (1'b0),
.RXPI_CFG0 (GTH4_RXPI_CFG0),
.RXPI_CFG1 (GTH4_RXPI_CFG1),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RXPI_LPM (1'b0),
.RXPI_SEL_LC (2'b00),
.RXPI_STARTCODE (2'b00),
@ -2481,7 +2478,7 @@ module util_adxcvr_xch #(
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.CH_HSPMUX (GTY4_CH_HSPMUX),
.CH_HSPMUX (CH_HSPMUX),
.CKCAL1_CFG_0 (16'b1100000011000000),
.CKCAL1_CFG_1 (16'b0001000011000000),
.CKCAL1_CFG_2 (16'b0010000000001000),
@ -2610,11 +2607,11 @@ module util_adxcvr_xch #(
.PD_TRANS_TIME_FROM_P2 (12'b000000111100),
.PD_TRANS_TIME_NONE_P2 (8'b00011001),
.PD_TRANS_TIME_TO_P2 (8'b01100100),
.PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST),
.RATE_SW_USE_DRP (1'b1),
.RCLK_SIPO_DLY_ENB (1'b0),
.RCLK_SIPO_INV_EN (1'b0),
.RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL),
.RTX_BUF_TERM_CTRL (2'b00),
.RXBUFRESET_TIME (5'b00011),
.RXBUF_ADDR_MODE ("FAST"),
@ -2734,7 +2731,7 @@ module util_adxcvr_xch #(
.RXPHSAMP_CFG (16'b0010000100000000),
.RXPHSLIP_CFG (16'b1001100100110011),
.RXPH_MONITOR_SEL (5'b00000),
.RXPI_CFG0 (GTY4_RXPI_CFG0),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (16'b0000000001010100),
.RXPMACLK_SEL ("DATA"),
.RXPMARESET_TIME (5'b00011),

5
library/xilinx/util_adxcvr/util_adxcvr_xcm.v
View File

@ -55,8 +55,7 @@ module util_adxcvr_xcm #(
parameter [15:0] QPLL_CFG4 = 16'b0000000000000011,
parameter [15:0] QPLL_CP_G3 = 10'b0000011111,
parameter [15:0] QPLL_LPF = 10'b0100110111,
parameter [15:0] QPLL_CP = 10'b0001111111,
parameter [15:0] GTY4_PPF0_CFG = 16'b0000100000000000
parameter [15:0] QPLL_CP = 10'b0001111111
) (
@ -557,7 +556,7 @@ module util_adxcvr_xcm #(
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (16'b0000000000000000),
.PPF0_CFG (GTY4_PPF0_CFG),
.PPF0_CFG (PPF0_CFG),
.PPF1_CFG (16'b0000011000000000),
.QPLL0CLKOUT_RATE ("HALF"),
.QPLL0_CFG0 (QPLL_CFG0),