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intel/adi_jesd204: Add an additional pipeline stage to RX soft PCS

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Istvan Csomortani 2020-04-21 14:38:36 +01:00 committed by István Csomortáni
parent 0e98527bad
commit 256593623c
2 changed files with 16 additions and 6 deletions
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6
library/intel/adi_jesd204/adi_jesd204_hw.tcl
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@ -127,7 +127,7 @@ ad_ip_parameter SOFT_PCS BOOLEAN true false { \
DISPLAY_NAME "Enable Soft PCS" \
}
ad_ip_parameter INPUT_PIPELINE BOOLEAN 0 false { \
ad_ip_parameter INPUT_PIPELINE_STAGES INTEGER 0 false { \
DISPLAY_NAME "Enable input pipeline" \
}
@ -296,7 +296,7 @@ proc jesd204_get_max_lane_rate {device soft_pcs} {
proc jesd204_validate {{quiet false}} {
set soft_pcs [get_parameter_value "SOFT_PCS"]
set input_pipeline [get_parameter_value "INPUT_PIPELINE"]
set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"]
set device_family [get_parameter_value "DEVICE_FAMILY"]
set device [get_parameter_value "DEVICE"]
set lane_rate [get_parameter_value "LANE_RATE"]
@ -347,7 +347,7 @@ proc jesd204_compose {} {
set device [get_parameter_value "DEVICE"]
set ext_device_clk_en [get_parameter_value "EXT_DEVICE_CLK_EN"]
set bonding_clocks_en [get_parameter_value "BONDING_CLOCKS_EN"]
set input_pipeline [get_parameter_value "INPUT_PIPELINE"]
set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"]
set pllclk_frequency [expr $lane_rate / 2]
set linkclk_frequency [expr $lane_rate / 40]

16
library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
View File

@ -88,7 +88,7 @@ end
generate
genvar lane;
genvar i;
if (REGISTER_INPUTS == 1) begin
if (REGISTER_INPUTS > 0) begin
reg patternalign_en_r;
reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_r;
always @(posedge clk) begin
@ -127,8 +127,18 @@ for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
localparam j = DATA_PATH_WIDTH * lane + i;
wire [9:0] in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] :
data_aligned[j*10+:10];
wire [9:0] in_char;
if (REGISTER_INPUTS > 1) begin
reg [9:0] in_char_r = 10'b0;
always @(posedge clk) begin
in_char_r <= INVERT_INPUTS ? ~data_aligned[j*10+:10] :
data_aligned[j*10+:10];
end
assign in_char = in_char_r;
end else begin
assign in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] :
data_aligned[j*10+:10];
end
jesd204_8b10b_decoder i_dec (
.in_char(in_char),