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util_clkdiv: Register output port as a clock (#33) 

If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
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Matthew Fornero 2017-06-19 02:40:53 -04:00 committed by István Csomortáni
parent 105b9e7114
commit 25a9949899
1 changed files with 3 additions and 0 deletions
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library/util_clkdiv/util_clkdiv_ip.tcl
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@ -22,4 +22,7 @@ set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters S
set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \
[list {"clk_out" "CLK"}]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]