diff --git a/library/axi_ad9122/axi_ad9122_dds.v b/library/axi_ad9122/axi_ad9122_dds.v
index a92ab9967..8f7e47e02 100755
--- a/library/axi_ad9122/axi_ad9122_dds.v
+++ b/library/axi_ad9122/axi_ad9122_dds.v
@@ -162,6 +162,7 @@ module axi_ad9122_dds (
   ad_dds i_dds_0 (
     .clk (dac_div_clk),
     .dds_format (dac_dds_format),
+    .dds_enable (dac_dds_enable),
     .dds_phase_0 (dac_dds_phase_0_0),
     .dds_scale_0 (dac_dds_scale_1),
     .dds_phase_1 (dac_dds_phase_0_1),
@@ -177,6 +178,7 @@ module axi_ad9122_dds (
   ad_dds i_dds_1 (
     .clk (dac_div_clk),
     .dds_format (dac_dds_format),
+    .dds_enable (dac_dds_enable),
     .dds_phase_0 (dac_dds_phase_1_0),
     .dds_scale_0 (dac_dds_scale_1),
     .dds_phase_1 (dac_dds_phase_1_1),
@@ -192,6 +194,7 @@ module axi_ad9122_dds (
   ad_dds i_dds_2 (
     .clk (dac_div_clk),
     .dds_format (dac_dds_format),
+    .dds_enable (dac_dds_enable),
     .dds_phase_0 (dac_dds_phase_2_0),
     .dds_scale_0 (dac_dds_scale_1),
     .dds_phase_1 (dac_dds_phase_2_1),
@@ -207,6 +210,7 @@ module axi_ad9122_dds (
   ad_dds i_dds_3 (
     .clk (dac_div_clk),
     .dds_format (dac_dds_format),
+    .dds_enable (dac_dds_enable),
     .dds_phase_0 (dac_dds_phase_3_0),
     .dds_scale_0 (dac_dds_scale_1),
     .dds_phase_1 (dac_dds_phase_3_1),
diff --git a/library/axi_ad9361/axi_ad9361_tx_dds.v b/library/axi_ad9361/axi_ad9361_tx_dds.v
index 28448e859..ac34c0f04 100755
--- a/library/axi_ad9361/axi_ad9361_tx_dds.v
+++ b/library/axi_ad9361/axi_ad9361_tx_dds.v
@@ -134,6 +134,7 @@ module axi_ad9361_tx_dds (
   ad_dds i_dds_0 (
     .clk (dac_clk),
     .dds_format (dac_dds_format),
+    .dds_enable (dac_dds_enable),
     .dds_phase_0 (dac_dds_phase_0),
     .dds_scale_0 (dac_dds_scale_1),
     .dds_phase_1 (dac_dds_phase_1),
diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v
index 227673c43..6f625dd0e 100644
--- a/library/common/ad_dds.v
+++ b/library/common/ad_dds.v
@@ -45,6 +45,7 @@ module ad_dds (
 
   clk,
   dds_format,
+  dds_enable,
   dds_phase_0,
   dds_scale_0,
   dds_phase_1,
@@ -55,6 +56,7 @@ module ad_dds (
 
   input           clk;
   input           dds_format;
+  input           dds_enable;
   input   [15:0]  dds_phase_0;
   input   [15:0]  dds_scale_0;
   input   [15:0]  dds_phase_1;
@@ -68,14 +70,21 @@ module ad_dds (
 
   // internal signals
 
+  wire    [15:0]  dds_data_int_s;
   wire    [15:0]  dds_data_0_s;
   wire    [15:0]  dds_data_1_s;
 
   // dds channel output
 
+  assign dds_data_int_s = {(dds_format ^ dds_data_int[15]), dds_data_int[14:0]};
+
   always @(posedge clk) begin
     dds_data_int <= dds_data_0_s + dds_data_1_s;
-    dds_data <= {(dds_format ^ dds_data_int[15]), dds_data_int[14:0]};
+    if (dds_enable == 1'b1) begin
+      dds_data <= dds_data_int_s;
+    end else begin
+      dds_data <= 16'd0;
+    end
   end
 
   // dds-1