projects/adrv9009zu11eg: JESD support for adrv2crr_fmc
for configurations 2, 4 TX_L and 2 RX/ORX_L Signed-off-by: LIacob106 <liviu.iacob@analog.com>main
LIacob106
AndrDragomir
parent
9b8604b9a2
commit
261c0d1b90
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@ -15,14 +15,20 @@ if {[info exists FMCOMMS8]} {
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set MAX_RX_OS_NUM_OF_LANES 4
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set MAX_RX_OS_NUM_OF_LANES 4
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}
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}
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set DATAPATH_WIDTH 4
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# TX parameters
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# TX parameters
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set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
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set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
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set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
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set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
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set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
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set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \
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set TX_TPL_WIDTH [ expr { [info exists ad_project_params(TX_TPL_WIDTH)] \
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($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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? $ad_project_params(TX_TPL_WIDTH) : {} } ]
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set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_NUM_OF_LANES $TX_NUM_OF_CONVERTERS $TX_SAMPLES_PER_FRAME $TX_SAMPLE_WIDTH $TX_TPL_WIDTH]
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8 * $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
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# RX parameters
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# RX parameters
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
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@ -30,8 +36,11 @@ set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
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set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
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set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \
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set RX_OCTETS_PER_FRAME [expr $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_FRAME * $RX_SAMPLE_WIDTH / (8 * $RX_NUM_OF_LANES)] ; # F
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($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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set DPW [expr max(4, $RX_OCTETS_PER_FRAME)] ; #max(4, F)
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8 * $DPW / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 8 * DPW / (M* N)
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set adc_dma_data_width [expr $RX_NUM_OF_LANES * 8 * $DPW]
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# RX Observation parameters
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# RX Observation parameters
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set RX_OS_NUM_OF_LANES $ad_project_params(RX_OS_JESD_L) ; # L
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set RX_OS_NUM_OF_LANES $ad_project_params(RX_OS_JESD_L) ; # L
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@ -39,8 +48,11 @@ set RX_OS_NUM_OF_CONVERTERS $ad_project_params(RX_OS_JESD_M) ; # M
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set RX_OS_SAMPLES_PER_FRAME $ad_project_params(RX_OS_JESD_S) ; # S
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set RX_OS_SAMPLES_PER_FRAME $ad_project_params(RX_OS_JESD_S) ; # S
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set RX_OS_SAMPLE_WIDTH 16 ; # N/NP
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set RX_OS_SAMPLE_WIDTH 16 ; # N/NP
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set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 32 / \
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set RX_OS_TPL_WIDTH [ expr { [info exists ad_project_params(RX_OS_TPL_WIDTH)] \
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($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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? $ad_project_params(RX_OS_TPL_WIDTH) : {} } ]
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set RX_OS_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_OS_NUM_OF_LANES $RX_OS_NUM_OF_CONVERTERS $RX_OS_SAMPLES_PER_FRAME $RX_OS_SAMPLE_WIDTH $RX_OS_TPL_WIDTH]
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set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 8 * $RX_OS_DATAPATH_WIDTH / ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)]
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set dac_fifo_name axi_tx_fifo
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set dac_fifo_name axi_tx_fifo
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set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
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set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
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@ -237,8 +249,6 @@ ad_connect ddr4_1_rstgen/peripheral_aresetn axi_tx_fifo/axi_resetn
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ad_connect sys_reset ddr4_1/sys_rst
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ad_connect sys_reset ddr4_1/sys_rst
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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ad_ip_instance axi_adxcvr axi_adrv9009_som_tx_xcvr
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ad_ip_instance axi_adxcvr axi_adrv9009_som_tx_xcvr
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ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.NUM_OF_LANES $MAX_TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.NUM_OF_LANES $MAX_TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.QPLL_ENABLE 1
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@ -276,6 +286,8 @@ ad_ip_parameter axi_adrv9009_som_rx_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_som_rx_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_adrv9009_som_rx_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_som_rx_jesd $RX_NUM_OF_LANES
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adi_axi_jesd204_rx_create axi_adrv9009_som_rx_jesd $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_som_rx_jesd/rx CONFIG.SYSREF_IOB false
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ad_ip_parameter axi_adrv9009_som_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $DPW
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ad_ip_instance util_cpack2 util_som_rx_cpack [list \
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ad_ip_instance util_cpack2 util_som_rx_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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@ -300,7 +312,8 @@ ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_som_rx_dma MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9009_som_rx_dma MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
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### This could be a problem
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance axi_adxcvr axi_adrv9009_som_obs_xcvr
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ad_ip_instance axi_adxcvr axi_adrv9009_som_obs_xcvr
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@ -382,16 +395,108 @@ if {[info exists FMCOMMS8]} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7 10 11 14 15} core_clk_a
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7 10 11 14 15} core_clk_a
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} else {
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} else {
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#ADRV2CRR_FMC
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#ADRV2CRR_FMC
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# Tx
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if {$TX_NUM_OF_LANES == 8} {
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if {$TX_NUM_OF_LANES == 8} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {} core_clk_a
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {} core_clk_a
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} else {
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} else {
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if {$TX_NUM_OF_LANES == 4} {
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#TX_JESD_L=4, it is recommanded to use RX_OS_JESD_M=TX_JESD_M because they share the same device clock
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#TX_JESD_L=4, it is recommanded to use RX_OS_JESD_M=TX_JESD_M because they share the same device clock
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7} core_clk_a {} $MAX_TX_NUM_OF_LANES {0 1 4 5}
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7} core_clk_a {} $MAX_TX_NUM_OF_LANES {0 1 4 5}
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} else {
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#TX_JESD_L=2
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7} core_clk_a {} $MAX_TX_NUM_OF_LANES {0 4}
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}
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}
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# Rx
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if {$RX_NUM_OF_LANES == 4} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5} core_clk_b
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} else {
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# for RX_JESD_L=2, RX_OCTETS_PER_FRAME = 8
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# 0 1 4 5 are the lanes for rx
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# find replacement for this
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#ad_connect adrv9009_rx_device_clk axi_adrv9009_rx_clkgen/clk_1
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#ad_connect adrv9009_rx_link_clk axi_adrv9009_rx_clkgen/clk_0
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#connect_bd_net [get_bd_pins util_adrv9009_som_xcvr/rx_out_clk_0] [get_bd_pins axi_adrv9009_som_rx_jesd/link_clk]
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_out_clk_0
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# core_clk_b is should be the link clock
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 2 3 4 5 6 7} adrv9009_som_rx_link_clk core_clk_b $MAX_RX_NUM_OF_LANES {0 4} 0
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_0 util_adrv9009_som_xcvr/up_es_0
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_1 util_adrv9009_som_xcvr/up_es_1
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_2 util_adrv9009_som_xcvr/up_es_4
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ad_connect axi_adrv9009_som_rx_xcvr/up_es_3 util_adrv9009_som_xcvr/up_es_5
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_0 util_adrv9009_som_xcvr/up_rx_0
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_1 util_adrv9009_som_xcvr/up_rx_1
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_2 util_adrv9009_som_xcvr/up_rx_4
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ad_connect axi_adrv9009_som_rx_xcvr/up_ch_3 util_adrv9009_som_xcvr/up_rx_5
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_0
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_1
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_4
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ad_connect adrv9009_som_rx_link_clk util_adrv9009_som_xcvr/rx_clk_5
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create_bd_port -dir I rx_data_0_p
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create_bd_port -dir I rx_data_0_n
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create_bd_port -dir I rx_data_1_p
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create_bd_port -dir I rx_data_1_n
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create_bd_port -dir I rx_data_4_p
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create_bd_port -dir I rx_data_4_n
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create_bd_port -dir I rx_data_5_p
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create_bd_port -dir I rx_data_5_n
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ad_connect util_adrv9009_som_xcvr/rx_0_p rx_data_0_p
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ad_connect util_adrv9009_som_xcvr/rx_0_n rx_data_0_n
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ad_connect util_adrv9009_som_xcvr/rx_1_p rx_data_1_p
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ad_connect util_adrv9009_som_xcvr/rx_1_n rx_data_1_n
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ad_connect util_adrv9009_som_xcvr/rx_4_p rx_data_4_p
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ad_connect util_adrv9009_som_xcvr/rx_4_n rx_data_4_n
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ad_connect util_adrv9009_som_xcvr/rx_5_p rx_data_5_p
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ad_connect util_adrv9009_som_xcvr/rx_5_n rx_data_5_n
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}
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# Rx -OBS
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if {$RX_OS_NUM_OF_LANES == 4} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7} core_clk_a
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} else {
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#ORX_JESD_L=2
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# 2 3 6 7 are the lanes for orx
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {0 1 2 3 4 5 6 7} core_clk_a {} $MAX_RX_OS_NUM_OF_LANES {2 6} 0
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_0 util_adrv9009_som_xcvr/up_es_2
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_1 util_adrv9009_som_xcvr/up_es_3
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_2 util_adrv9009_som_xcvr/up_es_6
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ad_connect axi_adrv9009_som_obs_xcvr/up_es_3 util_adrv9009_som_xcvr/up_es_7
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_0 util_adrv9009_som_xcvr/up_rx_2
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_1 util_adrv9009_som_xcvr/up_rx_3
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_2 util_adrv9009_som_xcvr/up_rx_6
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ad_connect axi_adrv9009_som_obs_xcvr/up_ch_3 util_adrv9009_som_xcvr/up_rx_7
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_2
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_3
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_6
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ad_connect core_clk_a util_adrv9009_som_xcvr/rx_clk_7
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create_bd_port -dir I rx_data_2_p
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create_bd_port -dir I rx_data_2_n
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create_bd_port -dir I rx_data_3_p
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create_bd_port -dir I rx_data_3_n
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create_bd_port -dir I rx_data_6_p
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create_bd_port -dir I rx_data_6_n
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create_bd_port -dir I rx_data_7_p
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create_bd_port -dir I rx_data_7_n
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ad_connect util_adrv9009_som_xcvr/rx_2_p rx_data_2_p
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ad_connect util_adrv9009_som_xcvr/rx_2_n rx_data_2_n
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ad_connect util_adrv9009_som_xcvr/rx_3_p rx_data_3_p
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ad_connect util_adrv9009_som_xcvr/rx_3_n rx_data_3_n
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ad_connect util_adrv9009_som_xcvr/rx_6_p rx_data_6_p
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ad_connect util_adrv9009_som_xcvr/rx_6_n rx_data_6_n
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ad_connect util_adrv9009_som_xcvr/rx_7_p rx_data_7_p
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ad_connect util_adrv9009_som_xcvr/rx_7_n rx_data_7_n
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}
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}
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5} core_clk_b
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7} core_clk_a
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}
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}
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##rx and orx stuff
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##ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5} core_clk_b
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##ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {2 3 6 7} core_clk_a
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ad_connect core_clk_a tx_adrv9009_som_tpl_core/link_clk
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ad_connect core_clk_a tx_adrv9009_som_tpl_core/link_clk
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ad_connect axi_adrv9009_som_tx_jesd/tx_data tx_adrv9009_som_tpl_core/link
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ad_connect axi_adrv9009_som_tx_jesd/tx_data tx_adrv9009_som_tpl_core/link
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@ -409,15 +514,26 @@ ad_connect tx_sysref_0 tx_adrv9009_som_tpl_core/dac_tpl_core/dac_sync_in
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# connections (adc)
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# connections (adc)
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ad_connect core_clk_b rx_adrv9009_som_tpl_core/link_clk
|
if {$RX_OCTETS_PER_FRAME == 8} {
|
||||||
|
# if this does not work, swap with link_clk
|
||||||
|
ad_connect core_clk_b rx_adrv9009_som_tpl_core/link_clk
|
||||||
|
ad_connect core_clk_b util_som_rx_cpack/clk
|
||||||
|
ad_connect axi_adrv9009_som_rx_dma/fifo_wr_clk core_clk_b
|
||||||
|
|
||||||
|
} else {
|
||||||
|
ad_connect core_clk_b rx_adrv9009_som_tpl_core/link_clk
|
||||||
|
ad_connect core_clk_b util_som_rx_cpack/clk
|
||||||
|
ad_connect axi_adrv9009_som_rx_dma/fifo_wr_clk core_clk_b
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
ad_connect axi_adrv9009_som_rx_jesd/rx_sof rx_adrv9009_som_tpl_core/link_sof
|
ad_connect axi_adrv9009_som_rx_jesd/rx_sof rx_adrv9009_som_tpl_core/link_sof
|
||||||
ad_connect axi_adrv9009_som_rx_jesd/rx_data_tdata rx_adrv9009_som_tpl_core/link_data
|
ad_connect axi_adrv9009_som_rx_jesd/rx_data_tdata rx_adrv9009_som_tpl_core/link_data
|
||||||
ad_connect axi_adrv9009_som_rx_jesd/rx_data_tvalid rx_adrv9009_som_tpl_core/link_valid
|
ad_connect axi_adrv9009_som_rx_jesd/rx_data_tvalid rx_adrv9009_som_tpl_core/link_valid
|
||||||
ad_connect core_clk_b util_som_rx_cpack/clk
|
|
||||||
ad_connect rx_adrv9009_som_tpl_core/adc_tpl_core/adc_rst util_som_rx_cpack/reset
|
ad_connect rx_adrv9009_som_tpl_core/adc_tpl_core/adc_rst util_som_rx_cpack/reset
|
||||||
ad_connect rx_adrv9009_som_tpl_core/adc_tpl_core/adc_sync_in rx_sysref_0
|
ad_connect rx_adrv9009_som_tpl_core/adc_tpl_core/adc_sync_in rx_sysref_0
|
||||||
|
|
||||||
|
|
||||||
ad_connect rx_adrv9009_som_tpl_core/adc_valid_0 util_som_rx_cpack/fifo_wr_en
|
ad_connect rx_adrv9009_som_tpl_core/adc_valid_0 util_som_rx_cpack/fifo_wr_en
|
||||||
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
|
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
|
||||||
ad_connect rx_adrv9009_som_tpl_core/adc_enable_$i util_som_rx_cpack/enable_$i
|
ad_connect rx_adrv9009_som_tpl_core/adc_enable_$i util_som_rx_cpack/enable_$i
|
||||||
|
|
@ -445,7 +561,6 @@ ad_connect util_som_obs_cpack/packed_fifo_wr axi_adrv9009_som_obs_dma/fifo_wr
|
||||||
|
|
||||||
ad_connect core_clk_a axi_adrv9009_som_tx_dma/m_axis_aclk
|
ad_connect core_clk_a axi_adrv9009_som_tx_dma/m_axis_aclk
|
||||||
|
|
||||||
ad_connect axi_adrv9009_som_rx_dma/fifo_wr_clk core_clk_b
|
|
||||||
ad_connect util_som_rx_cpack/packed_fifo_wr axi_adrv9009_som_rx_dma/fifo_wr
|
ad_connect util_som_rx_cpack/packed_fifo_wr axi_adrv9009_som_rx_dma/fifo_wr
|
||||||
|
|
||||||
ad_connect axi_tx_fifo/axi ddr4_1/C0_DDR4_S_AXI
|
ad_connect axi_tx_fifo/axi ddr4_1/C0_DDR4_S_AXI
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue