parent
47fa86cfd6
commit
26224186c1
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@ -104,7 +104,7 @@ module ad_dds #(
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sync_min_pulse_m[1] & !sync_min_pulse_m[CLK_RATIO];
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end
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for (i=1; i <= CLK_RATIO; i=i+1) begin: sync_delay
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for (i=1; i < CLK_RATIO; i=i+1) begin: sync_delay
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always @(posedge clk) begin
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sync_min_pulse_m[i+1] <= sync_min_pulse_m[i];
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end
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