ud_ip_jesd204_tpl_adc: update TPL instances

library/axi_ad6676/axi_ad6676.v

@@ -90,7 +90,10 @@ module axi_ad6676 #(
     .ID (ID),
     .NUM_LANES (NUM_LANES),
     .NUM_CHANNELS (2),
-    .CHANNEL_WIDTH (16),
+    .SAMPLES_PER_FRAME (1),
+    .CONVERTER_RESOLUTION (16),
+    .BITS_PER_SAMPLE (16),
+    .OCTETS_PER_BEAT (4),
     .TWOS_COMPLEMENT (0)
   ) i_adc_jesd204 (
     .link_clk (rx_clk),

library/axi_ad9250/axi_ad9250.v

@@ -89,7 +89,10 @@ module axi_ad9250 #(
     .ID (ID),
     .NUM_LANES (2),
     .NUM_CHANNELS (2),
-    .CHANNEL_WIDTH (14),
+    .SAMPLES_PER_FRAME (1),
+    .CONVERTER_RESOLUTION (14),
+    .BITS_PER_SAMPLE (16),
+    .OCTETS_PER_BEAT (4),
     .TWOS_COMPLEMENT (1)
   ) i_adc_jesd204 (
     .link_clk (rx_clk),

library/axi_ad9250/axi_ad9250_hw.tcl

@@ -15,6 +15,7 @@ set_module_property DISPLAY_NAME axi_ad9250
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9250
 add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
+add_fileset_file ad_perfect_shuffle.v VERILOG PATH $ad_hdl_dir/library/common/ad_perfect_shuffle.v
 add_fileset_file ad_pnmon.v           VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
 add_fileset_file ad_datafmt.v         VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
 add_fileset_file up_axi.v             VERILOG PATH $ad_hdl_dir/library/common/up_axi.v

library/axi_ad9680/axi_ad9680.v

@@ -87,9 +87,12 @@ module axi_ad9680 #(
 
   ad_ip_jesd204_tpl_adc #(
     .ID (ID),
-    .NUM_CHANNELS (2),
-    .CHANNEL_WIDTH (14),
     .NUM_LANES (4),
+    .NUM_CHANNELS (2),
+    .SAMPLES_PER_FRAME (1),
+    .CONVERTER_RESOLUTION (14),
+    .BITS_PER_SAMPLE (16),
+    .OCTETS_PER_BEAT (4),
     .TWOS_COMPLEMENT (1)
   ) i_adc_jesd204 (
     .link_clk (rx_clk),

library/axi_ad9680/axi_ad9680_hw.tcl

@@ -15,6 +15,7 @@ set_module_property DISPLAY_NAME axi_ad9680
 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9680
 add_fileset_file ad_rst.v             VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
+add_fileset_file ad_perfect_shuffle.v VERILOG PATH $ad_hdl_dir/library/common/ad_perfect_shuffle.v
 add_fileset_file ad_pnmon.v           VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
 add_fileset_file ad_datafmt.v         VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
 add_fileset_file up_axi.v             VERILOG PATH $ad_hdl_dir/library/common/up_axi.v