From 27b786e92fd07cedc5d2ea8a5ab323409e632fbd Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 3 Jul 2015 09:43:10 +0200 Subject: [PATCH] imageon_loopback: Use BUFIO for the HDMI clock buffer Since we are just doing a loopback all the logic is contained within the IO bank. By using a BUFIO instead of a BUFG we avoid having to route the clock signal from the IO bank to the middle of the FPGA and back to the IO bank. This reduces the skew between clock and the data signals and makes sure that the we can use the same design over a range of different resolutions without having to calibrate the delay. Signed-off-by: Lars-Peter Clausen --- projects/imageon_loopback/zed/system_top.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/projects/imageon_loopback/zed/system_top.v b/projects/imageon_loopback/zed/system_top.v index 2439d6129..55ab81679 100644 --- a/projects/imageon_loopback/zed/system_top.v +++ b/projects/imageon_loopback/zed/system_top.v @@ -173,18 +173,23 @@ module system_top ( wire hdmi_rx_clk; wire hdmi_tx_clk; + wire hdmi_rx_clk_bufio; wire [15:0] hdmi_rx_data; reg [15:0] hdmi_rx_data_in; reg [15:0] hdmi_tx_data; - always @(posedge hdmi_rx_clk) begin + always @(posedge hdmi_rx_clk_bufio) begin hdmi_rx_data_in <= hdmi_rx_data; hdmi_tx_data <= hdmi_rx_data_in; end // instantiations + BUFIO ( + .I (hdmi_rx_clk), + .O (hdmi_rx_clk_bufio)); + ODDR #(.INIT(1'b0)) i_clk_oddr ( .R (1'b0), .S (1'b0),