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daq3: update adcfifo/dacfifo

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Laszlo Nagy 2019-01-22 13:19:47 +00:00 committed by Laszlo Nagy
parent 9b048f1a0e
commit 27f1e4eaed
6 changed files with 19 additions and 18 deletions
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3
projects/daq3/a10gx/system_qsys.tcl
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@ -1,8 +1,5 @@
set dac_fifo_name avl_ad9152_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
source $ad_hdl_dir/projects/common/altera/dacfifo_qsys.tcl

14
projects/daq3/common/daq3_bd.tcl
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@ -1,6 +1,14 @@
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_fifo_name axi_ad9680_fifo
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9152_fifo
set dac_data_width 128
set dac_dma_data_width 128
# dac peripherals
ad_ip_instance axi_adxcvr axi_ad9152_xcvr
@ -30,6 +38,8 @@ ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
# adc peripherals
ad_ip_instance axi_adxcvr axi_ad9680_xcvr
@ -60,6 +70,10 @@ ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
if {$sys_zynq == 0 || $sys_zynq == 1} {
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
}
# shared transceiver core
ad_ip_instance util_adxcvr util_daq3_xcvr

5
projects/daq3/common/daq3_qsys.tcl
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@ -1,3 +1,6 @@
set dac_fifo_name avl_ad9152_fifo
set dac_data_width 128
set dac_dma_data_width 128
# ad9152-xcvr
@ -44,6 +47,8 @@ add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1
# dac fifo
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
add_interface tx_fifo_bypass conduit end
set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9152_fifo.if_bypass

6
projects/daq3/kcu105/system_bd.tcl
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@ -1,15 +1,9 @@
## FIFO depth is 4Mb - 250k samples
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
## FIFO depth is 4Mb - 250k samples
set dac_fifo_name axi_ad9152_fifo
set dac_fifo_address_width 15
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~70%

6
projects/daq3/zc706/system_bd.tcl
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@ -1,15 +1,9 @@
## FIFO depth is 1GB, PL_DDR is used
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
## FIFO depth is 8Mb - 500k samples
set dac_fifo_name axi_ad9152_fifo
set dac_fifo_address_width 16
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~47%

3
projects/daq3/zcu102/system_bd.tcl
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@ -1,9 +1,6 @@
## FIFO depth is 8Mb - 500k samples
set dac_fifo_name axi_ad9152_fifo
set dac_fifo_address_width 16
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~28%