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c5soc: dmac separated slave and master id widths

main
Rejeesh Kutty 2014-08-22 09:06:01 -04:00
parent f3f8414d81
commit 280260e54c
3 changed files with 246 additions and 249 deletions
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431
library/axi_dmac/axi_dmac_alt.v
View File

@ -83,27 +83,27 @@ module axi_dmac_alt (
// axi master interface (destination)
m_dest_axi_aclk,
m_dest_axi_aresetn,
m_dest_axi_awvalid,
m_dest_axi_awaddr,
m_dest_axi_aclk,
m_dest_axi_aresetn,
m_dest_axi_awvalid,
m_dest_axi_awaddr,
m_dest_axi_awid,
m_dest_axi_awlen,
m_dest_axi_awsize,
m_dest_axi_awburst,
m_dest_axi_awlen,
m_dest_axi_awsize,
m_dest_axi_awburst,
m_dest_axi_awlock,
m_dest_axi_awcache,
m_dest_axi_awprot,
m_dest_axi_awready,
m_dest_axi_wvalid,
m_dest_axi_wdata,
m_dest_axi_wstrb,
m_dest_axi_wlast,
m_dest_axi_wready,
m_dest_axi_bvalid,
m_dest_axi_bresp,
m_dest_axi_bid,
m_dest_axi_bready,
m_dest_axi_awcache,
m_dest_axi_awprot,
m_dest_axi_awready,
m_dest_axi_wvalid,
m_dest_axi_wdata,
m_dest_axi_wstrb,
m_dest_axi_wlast,
m_dest_axi_wready,
m_dest_axi_bvalid,
m_dest_axi_bresp,
m_dest_axi_bid,
m_dest_axi_bready,
m_dest_axi_arvalid,
m_dest_axi_araddr,
m_dest_axi_arid,
@ -123,73 +123,74 @@ module axi_dmac_alt (
// axi master interface (source)
m_src_axi_aclk,
m_src_axi_aresetn,
m_src_axi_awvalid,
m_src_axi_awaddr,
m_src_axi_aclk,
m_src_axi_aresetn,
m_src_axi_awvalid,
m_src_axi_awaddr,
m_src_axi_awid,
m_src_axi_awlen,
m_src_axi_awsize,
m_src_axi_awburst,
m_src_axi_awlen,
m_src_axi_awsize,
m_src_axi_awburst,
m_src_axi_awlock,
m_src_axi_awcache,
m_src_axi_awprot,
m_src_axi_awready,
m_src_axi_wvalid,
m_src_axi_wdata,
m_src_axi_wstrb,
m_src_axi_wlast,
m_src_axi_wready,
m_src_axi_bvalid,
m_src_axi_bresp,
m_src_axi_bid,
m_src_axi_bready,
m_src_axi_arvalid,
m_src_axi_araddr,
m_src_axi_awcache,
m_src_axi_awprot,
m_src_axi_awready,
m_src_axi_wvalid,
m_src_axi_wdata,
m_src_axi_wstrb,
m_src_axi_wlast,
m_src_axi_wready,
m_src_axi_bvalid,
m_src_axi_bresp,
m_src_axi_bid,
m_src_axi_bready,
m_src_axi_arvalid,
m_src_axi_araddr,
m_src_axi_arid,
m_src_axi_arlen,
m_src_axi_arsize,
m_src_axi_arburst,
m_src_axi_arlen,
m_src_axi_arsize,
m_src_axi_arburst,
m_src_axi_arlock,
m_src_axi_arcache,
m_src_axi_arprot,
m_src_axi_arready,
m_src_axi_rvalid,
m_src_axi_rresp,
m_src_axi_rdata,
m_src_axi_arcache,
m_src_axi_arprot,
m_src_axi_arready,
m_src_axi_rvalid,
m_src_axi_rresp,
m_src_axi_rdata,
m_src_axi_rid,
m_src_axi_rlast,
m_src_axi_rready,
m_src_axi_rready,
// axis
s_axis_aclk,
s_axis_ready,
s_axis_valid,
s_axis_data,
s_axis_user,
m_axis_aclk,
m_axis_ready,
m_axis_valid,
m_axis_data,
s_axis_aclk,
s_axis_ready,
s_axis_valid,
s_axis_data,
s_axis_user,
m_axis_aclk,
m_axis_ready,
m_axis_valid,
m_axis_data,
// fifo
fifo_wr_clk,
fifo_wr_en,
fifo_wr_din,
fifo_wr_overflow,
fifo_wr_sync,
fifo_rd_clk,
fifo_rd_en,
fifo_rd_valid,
fifo_rd_dout,
fifo_rd_underflow,
fifo_wr_clk,
fifo_wr_en,
fifo_wr_din,
fifo_wr_overflow,
fifo_wr_sync,
fifo_rd_clk,
fifo_rd_en,
fifo_rd_valid,
fifo_rd_dout,
fifo_rd_underflow,
irq);
parameter PCORE_ID = 0;
parameter PCORE_AXI_ID_WIDTH = 3;
parameter PCORE_AXIM_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_DMA_LENGTH_WIDTH = 14;
@ -246,30 +247,30 @@ module axi_dmac_alt (
// axi master interface (destination)
input m_dest_axi_aclk;
input m_dest_axi_aresetn;
output m_dest_axi_awvalid;
output [31:0] m_dest_axi_awaddr;
output [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_awid;
output [ 7:0] m_dest_axi_awlen;
output [ 2:0] m_dest_axi_awsize;
output [ 1:0] m_dest_axi_awburst;
input m_dest_axi_aclk;
input m_dest_axi_aresetn;
output m_dest_axi_awvalid;
output [31:0] m_dest_axi_awaddr;
output [(PCORE_AXIM_ID_WIDTH-1):0] m_dest_axi_awid;
output [ 7:0] m_dest_axi_awlen;
output [ 2:0] m_dest_axi_awsize;
output [ 1:0] m_dest_axi_awburst;
output [ 0:0] m_dest_axi_awlock;
output [ 3:0] m_dest_axi_awcache;
output [ 2:0] m_dest_axi_awprot;
input m_dest_axi_awready;
output m_dest_axi_wvalid;
output [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata;
output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb;
output m_dest_axi_wlast;
input m_dest_axi_wready;
input m_dest_axi_bvalid;
input [ 1:0] m_dest_axi_bresp;
input [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_bid;
output m_dest_axi_bready;
output [ 3:0] m_dest_axi_awcache;
output [ 2:0] m_dest_axi_awprot;
input m_dest_axi_awready;
output m_dest_axi_wvalid;
output [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata;
output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb;
output m_dest_axi_wlast;
input m_dest_axi_wready;
input m_dest_axi_bvalid;
input [ 1:0] m_dest_axi_bresp;
input [(PCORE_AXIM_ID_WIDTH-1):0] m_dest_axi_bid;
output m_dest_axi_bready;
output m_dest_axi_arvalid;
output [31:0] m_dest_axi_araddr;
output [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_arid;
output [(PCORE_AXIM_ID_WIDTH-1):0] m_dest_axi_arid;
output [ 7:0] m_dest_axi_arlen;
output [ 2:0] m_dest_axi_arsize;
output [ 1:0] m_dest_axi_arburst;
@ -280,74 +281,74 @@ module axi_dmac_alt (
input m_dest_axi_rvalid;
input [ 1:0] m_dest_axi_rresp;
input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata;
input [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_rid;
input [(PCORE_AXIM_ID_WIDTH-1):0] m_dest_axi_rid;
input m_dest_axi_rlast;
output m_dest_axi_rready;
// axi master interface (source)
input m_src_axi_aclk;
input m_src_axi_aresetn;
output m_src_axi_awvalid;
output [31:0] m_src_axi_awaddr;
output [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_awid;
output [ 7:0] m_src_axi_awlen;
output [ 2:0] m_src_axi_awsize;
output [ 1:0] m_src_axi_awburst;
input m_src_axi_aclk;
input m_src_axi_aresetn;
output m_src_axi_awvalid;
output [31:0] m_src_axi_awaddr;
output [(PCORE_AXIM_ID_WIDTH-1):0] m_src_axi_awid;
output [ 7:0] m_src_axi_awlen;
output [ 2:0] m_src_axi_awsize;
output [ 1:0] m_src_axi_awburst;
output [ 0:0] m_src_axi_awlock;
output [ 3:0] m_src_axi_awcache;
output [ 2:0] m_src_axi_awprot;
input m_src_axi_awready;
output m_src_axi_wvalid;
output [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata;
output [(C_DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb;
output m_src_axi_wlast;
input m_src_axi_wready;
input m_src_axi_bvalid;
input [ 1:0] m_src_axi_bresp;
input [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_bid;
output m_src_axi_bready;
output m_src_axi_arvalid;
output [31:0] m_src_axi_araddr;
output [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_arid;
output [ 7:0] m_src_axi_arlen;
output [ 2:0] m_src_axi_arsize;
output [ 1:0] m_src_axi_arburst;
output [ 3:0] m_src_axi_awcache;
output [ 2:0] m_src_axi_awprot;
input m_src_axi_awready;
output m_src_axi_wvalid;
output [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata;
output [(C_DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb;
output m_src_axi_wlast;
input m_src_axi_wready;
input m_src_axi_bvalid;
input [ 1:0] m_src_axi_bresp;
input [(PCORE_AXIM_ID_WIDTH-1):0] m_src_axi_bid;
output m_src_axi_bready;
output m_src_axi_arvalid;
output [31:0] m_src_axi_araddr;
output [(PCORE_AXIM_ID_WIDTH-1):0] m_src_axi_arid;
output [ 7:0] m_src_axi_arlen;
output [ 2:0] m_src_axi_arsize;
output [ 1:0] m_src_axi_arburst;
output [ 0:0] m_src_axi_arlock;
output [ 3:0] m_src_axi_arcache;
output [ 2:0] m_src_axi_arprot;
input m_src_axi_arready;
input m_src_axi_rvalid;
input [ 1:0] m_src_axi_rresp;
input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata;
input [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_rid;
output [ 3:0] m_src_axi_arcache;
output [ 2:0] m_src_axi_arprot;
input m_src_axi_arready;
input m_src_axi_rvalid;
input [ 1:0] m_src_axi_rresp;
input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata;
input [(PCORE_AXIM_ID_WIDTH-1):0] m_src_axi_rid;
input m_src_axi_rlast;
output m_src_axi_rready;
output m_src_axi_rready;
// axis
input s_axis_aclk;
output s_axis_ready;
input s_axis_valid;
input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data;
input [ 0:0] s_axis_user;
input m_axis_aclk;
input m_axis_ready;
output m_axis_valid;
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data;
input s_axis_aclk;
output s_axis_ready;
input s_axis_valid;
input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data;
input [ 0:0] s_axis_user;
input m_axis_aclk;
input m_axis_ready;
output m_axis_valid;
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data;
// fifo
input fifo_wr_clk;
input fifo_wr_en;
input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din;
output fifo_wr_overflow;
input fifo_wr_sync;
input fifo_rd_clk;
input fifo_rd_en;
output fifo_rd_valid;
output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout;
output fifo_rd_underflow;
input fifo_wr_clk;
input fifo_wr_en;
input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din;
output fifo_wr_overflow;
input fifo_wr_sync;
input fifo_rd_clk;
input fifo_rd_en;
output fifo_rd_valid;
output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout;
output fifo_rd_underflow;
output irq;
@ -377,77 +378,77 @@ module axi_dmac_alt (
.C_DMA_TYPE_DEST (C_DMA_TYPE_DEST),
.C_DMA_TYPE_SRC (C_DMA_TYPE_SRC))
i_axi_dmac (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awaddr ({18'd0, s_axi_awaddr}),
.s_axi_awready (s_axi_awready),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wready (s_axi_wready),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_araddr ({18'd0, s_axi_araddr}),
.s_axi_arready (s_axi_arready),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.irq (irq),
.m_dest_axi_aclk (m_dest_axi_aclk),
.m_dest_axi_aresetn (m_dest_axi_aresetn),
.m_src_axi_aclk (m_src_axi_aclk),
.m_src_axi_aresetn (m_src_axi_aresetn),
.m_dest_axi_awaddr (m_dest_axi_awaddr),
.m_dest_axi_awlen (m_dest_axi_awlen),
.m_dest_axi_awsize (m_dest_axi_awsize),
.m_dest_axi_awburst (m_dest_axi_awburst),
.m_dest_axi_awprot (m_dest_axi_awprot),
.m_dest_axi_awcache (m_dest_axi_awcache),
.m_dest_axi_awvalid (m_dest_axi_awvalid),
.m_dest_axi_awready (m_dest_axi_awready),
.m_dest_axi_wdata (m_dest_axi_wdata),
.m_dest_axi_wstrb (m_dest_axi_wstrb),
.m_dest_axi_wready (m_dest_axi_wready),
.m_dest_axi_wvalid (m_dest_axi_wvalid),
.m_dest_axi_wlast (m_dest_axi_wlast),
.m_dest_axi_bvalid (m_dest_axi_bvalid),
.m_dest_axi_bresp (m_dest_axi_bresp),
.m_dest_axi_bready (m_dest_axi_bready),
.m_src_axi_arready (m_src_axi_arready),
.m_src_axi_arvalid (m_src_axi_arvalid),
.m_src_axi_araddr (m_src_axi_araddr),
.m_src_axi_arlen (m_src_axi_arlen),
.m_src_axi_arsize (m_src_axi_arsize),
.m_src_axi_arburst (m_src_axi_arburst),
.m_src_axi_arprot (m_src_axi_arprot),
.m_src_axi_arcache (m_src_axi_arcache),
.m_src_axi_rdata (m_src_axi_rdata),
.m_src_axi_rready (m_src_axi_rready),
.m_src_axi_rvalid (m_src_axi_rvalid),
.m_src_axi_rresp (m_src_axi_rresp),
.s_axis_aclk (s_axis_aclk),
.s_axis_ready (s_axis_ready),
.s_axis_valid (s_axis_valid),
.s_axis_data (s_axis_data),
.s_axis_user (s_axis_user),
.m_axis_aclk (m_axis_aclk),
.m_axis_ready (m_axis_ready),
.m_axis_valid (m_axis_valid),
.m_axis_data (m_axis_data),
.fifo_wr_clk (fifo_wr_clk),
.fifo_wr_en (fifo_wr_en),
.fifo_wr_din (fifo_wr_din),
.fifo_wr_overflow (fifo_wr_overflow),
.fifo_wr_sync (fifo_wr_sync),
.fifo_rd_clk (fifo_rd_clk),
.fifo_rd_en (fifo_rd_en),
.fifo_rd_valid (fifo_rd_valid),
.fifo_rd_dout (fifo_rd_dout),
.fifo_rd_underflow (fifo_rd_underflow));
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awaddr ({18'd0, s_axi_awaddr}),
.s_axi_awready (s_axi_awready),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wready (s_axi_wready),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_araddr ({18'd0, s_axi_araddr}),
.s_axi_arready (s_axi_arready),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.irq (irq),
.m_dest_axi_aclk (m_dest_axi_aclk),
.m_dest_axi_aresetn (m_dest_axi_aresetn),
.m_src_axi_aclk (m_src_axi_aclk),
.m_src_axi_aresetn (m_src_axi_aresetn),
.m_dest_axi_awaddr (m_dest_axi_awaddr),
.m_dest_axi_awlen (m_dest_axi_awlen),
.m_dest_axi_awsize (m_dest_axi_awsize),
.m_dest_axi_awburst (m_dest_axi_awburst),
.m_dest_axi_awprot (m_dest_axi_awprot),
.m_dest_axi_awcache (m_dest_axi_awcache),
.m_dest_axi_awvalid (m_dest_axi_awvalid),
.m_dest_axi_awready (m_dest_axi_awready),
.m_dest_axi_wdata (m_dest_axi_wdata),
.m_dest_axi_wstrb (m_dest_axi_wstrb),
.m_dest_axi_wready (m_dest_axi_wready),
.m_dest_axi_wvalid (m_dest_axi_wvalid),
.m_dest_axi_wlast (m_dest_axi_wlast),
.m_dest_axi_bvalid (m_dest_axi_bvalid),
.m_dest_axi_bresp (m_dest_axi_bresp),
.m_dest_axi_bready (m_dest_axi_bready),
.m_src_axi_arready (m_src_axi_arready),
.m_src_axi_arvalid (m_src_axi_arvalid),
.m_src_axi_araddr (m_src_axi_araddr),
.m_src_axi_arlen (m_src_axi_arlen),
.m_src_axi_arsize (m_src_axi_arsize),
.m_src_axi_arburst (m_src_axi_arburst),
.m_src_axi_arprot (m_src_axi_arprot),
.m_src_axi_arcache (m_src_axi_arcache),
.m_src_axi_rdata (m_src_axi_rdata),
.m_src_axi_rready (m_src_axi_rready),
.m_src_axi_rvalid (m_src_axi_rvalid),
.m_src_axi_rresp (m_src_axi_rresp),
.s_axis_aclk (s_axis_aclk),
.s_axis_ready (s_axis_ready),
.s_axis_valid (s_axis_valid),
.s_axis_data (s_axis_data),
.s_axis_user (s_axis_user),
.m_axis_aclk (m_axis_aclk),
.m_axis_ready (m_axis_ready),
.m_axis_valid (m_axis_valid),
.m_axis_data (m_axis_data),
.fifo_wr_clk (fifo_wr_clk),
.fifo_wr_en (fifo_wr_en),
.fifo_wr_din (fifo_wr_din),
.fifo_wr_overflow (fifo_wr_overflow),
.fifo_wr_sync (fifo_wr_sync),
.fifo_rd_clk (fifo_rd_clk),
.fifo_rd_en (fifo_rd_en),
.fifo_rd_valid (fifo_rd_valid),
.fifo_rd_dout (fifo_rd_dout),
.fifo_rd_underflow (fifo_rd_underflow));
endmodule

23
library/axi_dmac/axi_dmac_hw.tcl
View File

@ -56,6 +56,13 @@ set_parameter_property PCORE_AXI_ID_WIDTH TYPE INTEGER
set_parameter_property PCORE_AXI_ID_WIDTH UNITS None
set_parameter_property PCORE_AXI_ID_WIDTH HDL_PARAMETER true
add_parameter PCORE_AXIM_ID_WIDTH INTEGER 0
set_parameter_property PCORE_AXIM_ID_WIDTH DEFAULT_VALUE 3
set_parameter_property PCORE_AXIM_ID_WIDTH DISPLAY_NAME PCORE_AXIM_ID_WIDTH
set_parameter_property PCORE_AXIM_ID_WIDTH TYPE INTEGER
set_parameter_property PCORE_AXIM_ID_WIDTH UNITS None
set_parameter_property PCORE_AXIM_ID_WIDTH HDL_PARAMETER true
add_parameter C_DMA_DATA_WIDTH_SRC INTEGER 0
set_parameter_property C_DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64
set_parameter_property C_DMA_DATA_WIDTH_SRC DISPLAY_NAME C_DMA_DATA_WIDTH_SRC
@ -241,7 +248,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2
add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST
add_interface_port m_dest_axi m_dest_axi_rready rready Output 1
add_interface_port m_dest_axi m_dest_axi_awid awid Output PCORE_AXI_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_awid awid Output PCORE_AXIM_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8
add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3
add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2
@ -249,15 +256,15 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4
add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3
add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1
add_interface_port m_dest_axi m_dest_axi_bid bid Input PCORE_AXI_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_arid arid Output PCORE_AXI_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_bid bid Input PCORE_AXIM_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_arid arid Output PCORE_AXIM_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8
add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3
add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2
add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1
add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4
add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
add_interface_port m_dest_axi m_dest_axi_rid rid Input PCORE_AXI_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_rid rid Input PCORE_AXIM_ID_WIDTH
add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1
}
@ -290,7 +297,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC
add_interface_port m_src_axi m_src_axi_rready rready Output 1
add_interface_port m_src_axi m_src_axi_awid awid Output PCORE_AXI_ID_WIDTH
add_interface_port m_src_axi m_src_axi_awid awid Output PCORE_AXIM_ID_WIDTH
add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
add_interface_port m_src_axi m_src_axi_awburst awburst Output 2
@ -298,15 +305,15 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_awcache awcache Output 4
add_interface_port m_src_axi m_src_axi_awprot awprot Output 3
add_interface_port m_src_axi m_src_axi_wlast wlast Output 1
add_interface_port m_src_axi m_src_axi_bid bid Input PCORE_AXI_ID_WIDTH
add_interface_port m_src_axi m_src_axi_arid arid Output PCORE_AXI_ID_WIDTH
add_interface_port m_src_axi m_src_axi_bid bid Input PCORE_AXIM_ID_WIDTH
add_interface_port m_src_axi m_src_axi_arid arid Output PCORE_AXIM_ID_WIDTH
add_interface_port m_src_axi m_src_axi_arlen arlen Output 8
add_interface_port m_src_axi m_src_axi_arsize arsize Output 3
add_interface_port m_src_axi m_src_axi_arburst arburst Output 2
add_interface_port m_src_axi m_src_axi_arlock arlock Output 1
add_interface_port m_src_axi m_src_axi_arcache arcache Output 4
add_interface_port m_src_axi m_src_axi_arprot arprot Output 3
add_interface_port m_src_axi m_src_axi_rid rid Input PCORE_AXI_ID_WIDTH
add_interface_port m_src_axi m_src_axi_rid rid Input PCORE_AXIM_ID_WIDTH
add_interface_port m_src_axi m_src_axi_rlast rlast Input 1
}

41
projects/fmcomms2/c5soc/system_bd.qsys
View File

@ -57,14 +57,6 @@
type = "String";
}
}
element sys_hps.f2h_axi_slave
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element sys_hps.f2h_sdram0_data
{
datum baseAddress
@ -73,14 +65,6 @@
type = "String";
}
}
element sys_int_mem.s1
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element sys_gpio.s1
{
datum _lockedAddress
@ -94,11 +78,11 @@
type = "String";
}
}
element axi_ad9361.s_axi
element sys_int_mem.s1
{
datum baseAddress
{
value = "131072";
value = "0";
type = "String";
}
}
@ -110,6 +94,14 @@
type = "String";
}
}
element axi_ad9361.s_axi
{
datum baseAddress
{
value = "131072";
type = "String";
}
}
element axi_dmac_adc.s_axi
{
datum baseAddress
@ -660,10 +652,10 @@
<parameter name="BSEL" value="1" />
<parameter name="CSEL_EN" value="false" />
<parameter name="CSEL" value="0" />
<parameter name="F2S_Width" value="2" />
<parameter name="F2S_Width" value="0" />
<parameter name="S2F_Width" value="2" />
<parameter name="LWH2F_Enable" value="true" />
<parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter>
<parameter name="F2SDRAM_Type" value="AXI-3" />
<parameter name="F2SDRAM_Width" value="64" />
<parameter name="BONDING_OUT_ENABLED" value="false" />
<parameter name="S2FCLK_COLDRST_Enable" value="false" />
@ -734,7 +726,7 @@
<parameter name="TRACE_Mode" value="N/A" />
<parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
<parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
<parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="F2H_AXI_CLOCK_FREQ" value="100" />
<parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="F2H_SDRAM0_CLOCK_FREQ" value="80000000" />
@ -853,6 +845,7 @@
<module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_dac">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="12" />
<parameter name="PCORE_AXIM_ID_WIDTH" value="3" />
<parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
<parameter name="C_DMA_LENGTH_WIDTH" value="14" />
@ -871,6 +864,7 @@
<module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_adc">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="12" />
<parameter name="PCORE_AXIM_ID_WIDTH" value="3" />
<parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
<parameter name="C_DMA_LENGTH_WIDTH" value="14" />
@ -886,11 +880,6 @@
<parameter name="C_DMA_TYPE_SRC" value="2" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
</module>
<connection
kind="clock"
version="14.0"
start="sys_clk.clk"
end="sys_hps.f2h_axi_clock" />
<connection
kind="avalon"
version="14.0"