From 283bf9ad75b126989593390e6f9a35e4fb0e5ff1 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 11 Jul 2016 18:37:18 +0300 Subject: [PATCH] fmcomms2_a10GX: Add fmcomms2 on a10gx --- projects/fmcomms2/a10gx/Makefile | 150 +++++++++++++ projects/fmcomms2/a10gx/system_constr.sdc | 17 ++ projects/fmcomms2/a10gx/system_project.tcl | 117 ++++++++++ projects/fmcomms2/a10gx/system_qsys.tcl | 7 + projects/fmcomms2/a10gx/system_top.v | 250 +++++++++++++++++++++ 5 files changed, 541 insertions(+) create mode 100644 projects/fmcomms2/a10gx/Makefile create mode 100644 projects/fmcomms2/a10gx/system_constr.sdc create mode 100644 projects/fmcomms2/a10gx/system_project.tcl create mode 100644 projects/fmcomms2/a10gx/system_qsys.tcl create mode 100644 projects/fmcomms2/a10gx/system_top.v diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile new file mode 100644 index 000000000..e72b8c54f --- /dev/null +++ b/projects/fmcomms2/a10gx/Makefile @@ -0,0 +1,150 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_qsys.tcl +M_DEPS += system_project.tcl +M_DEPS += system_constr.sdc +M_DEPS += ../common/fmcomms2_qsys.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl +M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v +M_DEPS += ../../../library/axi_dmac/2d_transfer.v +M_DEPS += ../../../library/axi_dmac/address_generator.v +M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl +M_DEPS += ../../../library/axi_dmac/axi_register_slice.v +M_DEPS += ../../../library/axi_dmac/data_mover.v +M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v +M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v +M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v +M_DEPS += ../../../library/axi_dmac/inc_id.h +M_DEPS += ../../../library/axi_dmac/request_arb.v +M_DEPS += ../../../library/axi_dmac/request_generator.v +M_DEPS += ../../../library/axi_dmac/resp.h +M_DEPS += ../../../library/axi_dmac/response_generator.v +M_DEPS += ../../../library/axi_dmac/response_handler.v +M_DEPS += ../../../library/axi_dmac/splitter.v +M_DEPS += ../../../library/axi_dmac/src_axi_mm.v +M_DEPS += ../../../library/axi_dmac/src_axi_stream.v +M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v +M_DEPS += ../../../library/common/ad_addsub.v +M_DEPS += ../../../library/common/ad_datafmt.v +M_DEPS += ../../../library/common/ad_dcfilter.v +M_DEPS += ../../../library/common/ad_dds.v +M_DEPS += ../../../library/common/ad_dds_1.v +M_DEPS += ../../../library/common/ad_dds_sine.v +M_DEPS += ../../../library/common/ad_iqcor.v +M_DEPS += ../../../library/common/ad_mem.v +M_DEPS += ../../../library/common/ad_mul.v +M_DEPS += ../../../library/common/ad_pnmon.v +M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_tdd_control.v +M_DEPS += ../../../library/common/altera/DSP48E1.v +M_DEPS += ../../../library/common/altera/MULT_MACRO.v +M_DEPS += ../../../library/common/altera/ad_cmos_clk.v +M_DEPS += ../../../library/common/altera/ad_cmos_in.v +M_DEPS += ../../../library/common/altera/ad_cmos_out.v +M_DEPS += ../../../library/common/altera/ad_lvds_clk.v +M_DEPS += ../../../library/common/altera/ad_lvds_in.v +M_DEPS += ../../../library/common/altera/ad_lvds_out.v +M_DEPS += ../../../library/common/sync_bits.v +M_DEPS += ../../../library/common/sync_gray.v +M_DEPS += ../../../library/common/up_adc_channel.v +M_DEPS += ../../../library/common/up_adc_common.v +M_DEPS += ../../../library/common/up_axi.v +M_DEPS += ../../../library/common/up_clock_mon.v +M_DEPS += ../../../library/common/up_dac_channel.v +M_DEPS += ../../../library/common/up_dac_common.v +M_DEPS += ../../../library/common/up_delay_cntrl.v +M_DEPS += ../../../library/common/up_tdd_cntrl.v +M_DEPS += ../../../library/common/up_xfer_cntrl.v +M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/common/util_pulse_gen.v +M_DEPS += ../../../library/util_axis_fifo/address_gray.v +M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v +M_DEPS += ../../../library/util_axis_fifo/address_sync.v +M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v +M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v +M_DEPS += ../../../library/util_cpack/util_cpack.v +M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v +M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl +M_DEPS += ../../../library/util_cpack/util_cpack_mux.v +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.v +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync_hw.tcl +M_DEPS += ../../../library/util_upack/util_upack.v +M_DEPS += ../../../library/util_upack/util_upack_dmx.v +M_DEPS += ../../../library/util_upack/util_upack_dsf.v +M_DEPS += ../../../library/util_upack/util_upack_hw.tcl +M_DEPS += ../../../library/util_wfifo/util_wfifo.v +M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl + + +M_ALTERA := quartus_sh --64bit -t + + +M_FLIST += *.log +M_FLIST += *_INFO.txt +M_FLIST += *_dump.txt +M_FLIST += db +M_FLIST += *.asm.rpt +M_FLIST += *.done +M_FLIST += *.eda.rpt +M_FLIST += *.fit.* +M_FLIST += *.map.* +M_FLIST += *.sta.* +M_FLIST += *.qsf +M_FLIST += *.qpf +M_FLIST += *.qws +M_FLIST += *.sof +M_FLIST += *.cdf +M_FLIST += *.sld +M_FLIST += *.qdf +M_FLIST += hc_output +M_FLIST += system_bd +M_FLIST += hps_isw_handoff +M_FLIST += hps_sdram_*.csv +M_FLIST += *ddr3_*.csv +M_FLIST += incremental_db +M_FLIST += reconfig_mif +M_FLIST += *.sopcinfo +M_FLIST += *.jdi +M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf + + + +.PHONY: all clean clean-all +all: fmcomms2_a10gx.sof + + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +fmcomms2_a10gx.sof: $(M_DEPS) + rm -rf $(M_FLIST) + $(M_ALTERA) system_project.tcl >> fmcomms2_a10gx_quartus.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/projects/fmcomms2/a10gx/system_constr.sdc b/projects/fmcomms2/a10gx/system_constr.sdc new file mode 100644 index 000000000..6274154c7 --- /dev/null +++ b/projects/fmcomms2/a10gx/system_constr.sdc @@ -0,0 +1,17 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "4.000 ns" -name rx_clk_250mhz [get_ports {rx_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ + i_system_bd|sys_ddr3_cntrl_phy_clk_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_2 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}] + +set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ + i_system_bd|sys_ddr3_cntrl_core_nios_clk}] diff --git a/projects/fmcomms2/a10gx/system_project.tcl b/projects/fmcomms2/a10gx/system_project.tcl new file mode 100644 index 000000000..903b406b3 --- /dev/null +++ b/projects/fmcomms2/a10gx/system_project.tcl @@ -0,0 +1,117 @@ + +load_package flow + +source ../../scripts/adi_env.tcl +project_new fmcomms2_a10gx -overwrite + +source "../../common/a10gx/a10gx_system_assign.tcl" + +set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys + +set_global_assignment -name SDC_FILE system_constr.sdc +set_global_assignment -name TOP_LEVEL_ENTITY system_top + +# lane interface + +set_location_assignment PIN_AV15 -to rx_clk_in ; ## G6 FMC_LPC_LA00_CC_P +set_location_assignment PIN_AU15 -to "rx_clk_in(n)" ; ## G7 FMC_LPC_LA00_CC_N +set_location_assignment PIN_AT10 -to rx_frame_in ; ## D8 FMC_LPC_LA01_CC_P +set_location_assignment PIN_AR11 -to "rx_frame_in(n)" ; ## D9 FMC_LPC_LA01_CC_N +set_location_assignment PIN_AR22 -to rx_data_in[0] ; ## H7 FMC_LPC_LA02_P +set_location_assignment PIN_AT22 -to "rx_data_in[0](n)" ; ## H8 FMC_LPC_LA02_N +set_location_assignment PIN_AR20 -to rx_data_in[1] ; ## G9 FMC_LPC_LA03_P +set_location_assignment PIN_AR19 -to "rx_data_in[1](n)" ; ## G10 FMC_LPC_LA03_N +set_location_assignment PIN_AN20 -to rx_data_in[2] ; ## H10 FMC_LPC_LA04_P +set_location_assignment PIN_AP19 -to "rx_data_in[2](n)" ; ## H11 FMC_LPC_LA04_N +set_location_assignment PIN_AV11 -to rx_data_in[3] ; ## D11 FMC_LPC_LA05_P +set_location_assignment PIN_AW11 -to "rx_data_in[3](n)" ; ## D12 FMC_LPC_LA05_N +set_location_assignment PIN_AV14 -to rx_data_in[4] ; ## C10 FMC_LPC_LA06_P +set_location_assignment PIN_AW14 -to "rx_data_in[4](n)" ; ## C11 FMC_LPC_LA06_N +set_location_assignment PIN_AT17 -to rx_data_in[5] ; ## H13 FMC_LPC_LA07_P +set_location_assignment PIN_AU17 -to "rx_data_in[5](n)" ; ## H14 FMC_LPC_LA07_N +set_location_assignment PIN_AP18 -to tx_clk_out ; ## G12 FMC_LPC_LA08_P +set_location_assignment PIN_AN19 -to "tx_clk_out(n)" ; ## G13 FMC_LPC_LA08_N +set_location_assignment PIN_AW13 -to tx_frame_out ; ## D14 FMC_LPC_LA09_P +set_location_assignment PIN_AV13 -to "tx_frame_out(n)" ; ## D15 FMC_LPC_LA09_N +set_location_assignment PIN_AT14 -to tx_data_out[0] ; ## H16 FMC_LPC_LA11_P +set_location_assignment PIN_AR14 -to "tx_data_out[0](n)" ; ## H17 FMC_LPC_LA11_N +set_location_assignment PIN_AR16 -to tx_data_out[1] ; ## G15 FMC_LPC_LA12_P +set_location_assignment PIN_AP16 -to "tx_data_out[1](n)" ; ## G16 FMC_LPC_LA12_N +set_location_assignment PIN_AR17 -to tx_data_out[2] ; ## D17 FMC_LPC_LA13_P +set_location_assignment PIN_AP17 -to "tx_data_out[2](n)" ; ## D18 FMC_LPC_LA13_N +set_location_assignment PIN_AR15 -to tx_data_out[3] ; ## C14 FMC_LPC_LA10_P +set_location_assignment PIN_AT15 -to "tx_data_out[3](n)" ; ## C15 FMC_LPC_LA10_N +set_location_assignment PIN_AW18 -to tx_data_out[4] ; ## C18 FMC_LPC_LA14_P +set_location_assignment PIN_AV18 -to "tx_data_out[4](n)" ; ## C19 FMC_LPC_LA14_N +set_location_assignment PIN_AR9 -to tx_data_out[5] ; ## H19 FMC_LPC_LA15_P +set_location_assignment PIN_AT9 -to "tx_data_out[5](n)" ; ## H20 FMC_LPC_LA15_N +set_location_assignment PIN_AT13 -to enable] ; ## G18 FMC_LPC_LA16_P +set_location_assignment PIN_AU13 -to txnrx] ; ## G19 FMC_LPC_LA16_N + +set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in +set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[1] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[2] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[3] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[4] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[5] +set_instance_assignment -name IO_STANDARD LVDS -to tx_clk_out +set_instance_assignment -name IO_STANDARD LVDS -to tx_frame_out +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[0] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[1] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5] +set_instance_assignment -name IO_STANDARD LVDS -to enable +set_instance_assignment -name IO_STANDARD LVDS -to txnrx + +# gpio + +set_location_assignment PIN_AU8 -to gpio_status[0] ; ## G21 FMC_LPC_LA20_P +set_location_assignment PIN_AT8 -to gpio_status[1] ; ## G22 FMC_LPC_LA20_N +set_location_assignment PIN_AY10 -to gpio_status[2] ; ## H25 FMC_LPC_LA21_P +set_location_assignment PIN_AY11 -to gpio_status[3] ; ## H26 FMC_LPC_LA21_N +set_location_assignment PIN_AW12 -to gpio_status[4] ; ## G24 FMC_LPC_LA22_P +set_location_assignment PIN_AY12 -to gpio_status[5] ; ## G25 FMC_LPC_LA22_N +set_location_assignment PIN_AU18 -to gpio_status[6] ; ## D23 FMC_LPC_LA23_P +set_location_assignment PIN_AT18 -to gpio_status[7] ; ## D24 FMC_LPC_LA23_N +set_location_assignment PIN_BB15 -to gpio_ctl[0] ; ## H28 FMC_LPC_LA24_P +set_location_assignment PIN_BC15 -to gpio_ctl[1] ; ## H29 FMC_LPC_LA24_N +set_location_assignment PIN_AY15 -to gpio_ctl[2] ; ## G27 FMC_LPC_LA25_P +set_location_assignment PIN_AY14 -to gpio_ctl[3] ; ## G28 FMC_LPC_LA25_N +set_location_assignment PIN_AU11 -to gpio_en_agc ; ## H22 FMC_LPC_LA19_P +set_location_assignment PIN_AU12 -to gpio_sync ; ## H23 FMC_LPC_LA19_N +set_location_assignment PIN_AY16 -to gpio_resetb ; ## H31 FMC_LPC_LA28_P + +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_en_agc +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_sync +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_resetb + +# spi + +set_location_assignment PIN_AT19 -to spi_csn ; ## D26 FMC_LPC_LA26_P +set_location_assignment PIN_AT20 -to spi_clk ; ## D27 FMC_LPC_LA26_N +set_location_assignment PIN_AP21 -to spi_mosi ; ## C26 FMC_LPC_LA27_P +set_location_assignment PIN_AR21 -to spi_miso ; ## C27 FMC_LPC_LA27_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso + +execute_flow -compile diff --git a/projects/fmcomms2/a10gx/system_qsys.tcl b/projects/fmcomms2/a10gx/system_qsys.tcl new file mode 100644 index 000000000..07a5e1a90 --- /dev/null +++ b/projects/fmcomms2/a10gx/system_qsys.tcl @@ -0,0 +1,7 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl +source ../common/fmcomms2_qsys.tcl + +save_system "system_bd.qsys" + diff --git a/projects/fmcomms2/a10gx/system_top.v b/projects/fmcomms2/a10gx/system_top.v new file mode 100644 index 000000000..b326ff43a --- /dev/null +++ b/projects/fmcomms2/a10gx/system_top.v @@ -0,0 +1,250 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + sys_clk, + sys_resetn, + + // ddr3 + + ddr3_clk_p, + ddr3_clk_n, + ddr3_a, + ddr3_ba, + ddr3_cke, + ddr3_cs_n, + ddr3_odt, + ddr3_reset_n, + ddr3_we_n, + ddr3_ras_n, + ddr3_cas_n, + ddr3_dqs_p, + ddr3_dqs_n, + ddr3_dq, + ddr3_dm, + ddr3_rzq, + ddr3_ref_clk, + + // ethernet + + eth_ref_clk, + eth_rxd, + eth_txd, + eth_mdc, + eth_mdio, + eth_resetn, + eth_intn, + + // board gpio + + gpio_bd_i, + gpio_bd_o, + + // ad9361-interface + + rx_clk_in, + rx_frame_in, + rx_data_in, + tx_clk_out, + tx_frame_out, + tx_data_out, + + enable, + txnrx, + + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + + // clock and resets + + input sys_clk; + input sys_resetn; + + // ddr3 + + output ddr3_clk_p; + output ddr3_clk_n; + output [ 14:0] ddr3_a; + output [ 2:0] ddr3_ba; + output ddr3_cke; + output ddr3_cs_n; + output ddr3_odt; + output ddr3_reset_n; + output ddr3_we_n; + output ddr3_ras_n; + output ddr3_cas_n; + inout [ 7:0] ddr3_dqs_p; + inout [ 7:0] ddr3_dqs_n; + inout [ 63:0] ddr3_dq; + output [ 7:0] ddr3_dm; + input ddr3_rzq; + input ddr3_ref_clk; + + // ethernet + + input eth_ref_clk; + input eth_rxd; + output eth_txd; + output eth_mdc; + inout eth_mdio; + output eth_resetn; + input eth_intn; + + // board gpio + + input [ 10:0] gpio_bd_i; + output [ 15:0] gpio_bd_o; + + // ad9361-interface + + input rx_clk_in; + input rx_frame_in; + input [ 5:0] rx_data_in; + output tx_clk_out; + output tx_frame_out; + output [ 5:0] tx_data_out; + output enable; + output txnrx; + + output gpio_resetb; + output gpio_sync; + output gpio_en_agc; + output [ 3:0] gpio_ctl; + input [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // conections + + assign gpio_resetb = gpio_o[46]; + assign gpio_sync = gpio_o[45]; + assign gpio_en_agc = gpio_o[44]; + assign gpio_ctl = gpio_o[43:40]; + assign gpio_i[39:32] = gpio_status; + + assign gpio_bd_o = gpio_o[15:0]; + + assign gpio_i[31:27] = gpio_o[31:27]; + assign gpio_i[15: 0] = gpio_o[15:0]; + assign gpio_i[26:16] = gpio_bd_i; + + // instantiations + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_rst_reset_n (sys_resetn), + + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_ref_clk_clk (eth_ref_clk), + .sys_ethernet_reset_reset (eth_reset), + .sys_ethernet_sgmii_rxp_0 (eth_rxd), + .sys_ethernet_sgmii_txp_0 (eth_txd), + + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .axi_ad9361_device_if_enable (enable), + .axi_ad9361_device_if_rx_clk_in_p (rx_clk_in), + .axi_ad9361_device_if_rx_clk_in_n (1'b0), + .axi_ad9361_device_if_rx_data_in_p (rx_data_in), + .axi_ad9361_device_if_rx_data_in_n (6'd0), + .axi_ad9361_device_if_rx_frame_in_p (rx_frame_in), + .axi_ad9361_device_if_rx_frame_in_n (1'b0), + .axi_ad9361_device_if_tx_clk_out_p (tx_clk_out), + .axi_ad9361_device_if_tx_clk_out_n (1'b0), + .axi_ad9361_device_if_tx_data_out_p (tx_data_out), + .axi_ad9361_device_if_tx_data_out_n (6'd0), + .axi_ad9361_device_if_tx_frame_out_p (tx_frame_out), + .axi_ad9361_device_if_tx_frame_out_n (1'b0), + .axi_ad9361_device_if_txnrx (txnrx), + + .delay_clk_clk (1'b0), + + .up_enable_up_enable (gpio_o[47]), + .up_txnrx_up_txnrx (gpio_o[48])); + +endmodule + + +// *************************************************************************** +// ***************************************************************************