From 287770a201f87fb212df41dd4db758cb06171836 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 8 Mar 2016 10:44:58 +0100 Subject: [PATCH] axi_dmac: Fix tlast generation on AXI stream master For the AXI stream interface we want to generate TLAST only at the end of the transfer, rather than at the end of each burst. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/data_mover.v | 4 +++- library/axi_dmac/dest_axi_stream.v | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index 0c883d5fd..714e28cb2 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -68,6 +68,8 @@ parameter ID_WIDTH = 3; parameter DATA_WIDTH = 64; parameter DISABLE_WAIT_FOR_ID = 1; parameter BEATS_PER_BURST_WIDTH = 4; +parameter LAST = 0; /* 0 = last asserted at the end of each burst, 1 = last only asserted at the end of the transfer */ + localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH); `include "inc_id.h" @@ -94,7 +96,7 @@ assign last = eot ? last_eot : last_non_eot; assign s_axi_ready = m_axi_ready & pending_burst & active; assign m_axi_valid = s_axi_valid & pending_burst & active; assign m_axi_data = s_axi_data; -assign m_axi_last = last; +assign m_axi_last = LAST ? (last_eot & eot) : last; // If we want to support zero delay between transfers we have to assert // req_ready on the same cycle on which the last load happens. diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v index a72a24e80..48c5dea55 100644 --- a/library/axi_dmac/dest_axi_stream.v +++ b/library/axi_dmac/dest_axi_stream.v @@ -100,7 +100,8 @@ dmac_data_mover # ( .ID_WIDTH(ID_WIDTH), .DATA_WIDTH(S_AXIS_DATA_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), - .DISABLE_WAIT_FOR_ID(0) + .DISABLE_WAIT_FOR_ID(0), + .LAST(1) ) i_data_mover ( .clk(s_axis_aclk), .resetn(s_axis_aresetn),