From 28801f2f37f38317aea507844e09d40f7aeac61a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 28 Jul 2017 19:11:03 +0200 Subject: [PATCH] common: a10soc: Use correct DDR memory reference clock type The DDR memory reference clock on the A10SoC development board is differential. Currently the EMIF core it is configured for single-ended configuration, which causes it to generate incorrect IOSTANDARD constraints. Those incorrect constraints get overwritten again in system_assign.tcl, so things are working, but this generates a warning when building the design Configure the EMIF core correctly and remove the manual constraint overwrite since they are no longer necessary. Signed-off-by: Lars-Peter Clausen --- projects/common/a10soc/a10soc_system_assign.tcl | 5 ----- projects/common/a10soc/a10soc_system_qsys.tcl | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl index cf2a0cc10..a053c3136 100644 --- a/projects/common/a10soc/a10soc_system_assign.tcl +++ b/projects/common/a10soc/a10soc_system_assign.tcl @@ -12,11 +12,6 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn set_location_assignment PIN_F25 -to hps_ddr_ref_clk set_location_assignment PIN_G24 -to "hps_ddr_ref_clk(n)" - -set_instance_assignment -name IO_STANDARD LVDS -to hps_ddr_ref_clk -set_instance_assignment -name IO_STANDARD LVDS -to "hps_ddr_ref_clk(n)" -set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to hps_ddr_ref_clk -disable - set_location_assignment PIN_B20 -to hps_ddr_clk_p set_location_assignment PIN_B19 -to hps_ddr_clk_n set_location_assignment PIN_B26 -to hps_ddr_a[0] diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl index b5a29f7f8..939a31cb0 100644 --- a/projects/common/a10soc/a10soc_system_qsys.tcl +++ b/projects/common/a10soc/a10soc_system_qsys.tcl @@ -149,7 +149,7 @@ set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_MODE_ENUM} {OU set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12} set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL} set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL} -set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_CMOS_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_LVDS_NO_OCT} set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12} set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666} set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRCD_NS} {14.25}