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common: a10soc: Use correct DDR memory reference clock type 

The DDR memory reference clock on the A10SoC development board is
differential. Currently the EMIF core it is configured for single-ended
configuration, which causes it to generate incorrect IOSTANDARD
constraints. Those incorrect constraints get overwritten again in
system_assign.tcl, so things are working, but this generates a warning when
building the design

Configure the EMIF core correctly and remove the manual constraint overwrite since
they are no longer necessary.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-28 19:11:03 +02:00
parent 15c3c96512
commit 28801f2f37
2 changed files with 1 additions and 6 deletions
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5
projects/common/a10soc/a10soc_system_assign.tcl
View File

@ -12,11 +12,6 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn
set_location_assignment PIN_F25 -to hps_ddr_ref_clk set_location_assignment PIN_F25 -to hps_ddr_ref_clk
set_location_assignment PIN_G24 -to "hps_ddr_ref_clk(n)" set_location_assignment PIN_G24 -to "hps_ddr_ref_clk(n)"
set_instance_assignment -name IO_STANDARD LVDS -to hps_ddr_ref_clk
set_instance_assignment -name IO_STANDARD LVDS -to "hps_ddr_ref_clk(n)"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to hps_ddr_ref_clk -disable
set_location_assignment PIN_B20 -to hps_ddr_clk_p set_location_assignment PIN_B20 -to hps_ddr_clk_p
set_location_assignment PIN_B19 -to hps_ddr_clk_n set_location_assignment PIN_B19 -to hps_ddr_clk_n
set_location_assignment PIN_B26 -to hps_ddr_a[0] set_location_assignment PIN_B26 -to hps_ddr_a[0]

2
projects/common/a10soc/a10soc_system_qsys.tcl
View File

@ -149,7 +149,7 @@ set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_MODE_ENUM} {OU
set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12} set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12}
set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL} set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL}
set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL} set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL}
set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_CMOS_12} set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_LVDS_NO_OCT}
set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12} set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12}
set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666} set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666}
set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRCD_NS} {14.25} set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRCD_NS} {14.25}