From 28ace647d10f24ba0c32594a37d0a64e19e1c04a Mon Sep 17 00:00:00 2001 From: alin724 Date: Thu, 29 Sep 2022 08:26:51 +0300 Subject: [PATCH] up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module --- docs/regmap/adi_regmap_adc.txt | 32 +++++++++++++++++++ library/axi_ad7768/axi_ad7768.v | 5 +++ library/axi_ad777x/axi_ad777x.v | 5 +++ library/axi_ad9265/axi_ad9265.v | 17 +++++++++- library/axi_ad9361/axi_ad9361_rx.v | 15 +++++++-- library/axi_ad9434/axi_ad9434_core.v | 15 +++++++++ library/axi_ad9467/axi_ad9467.v | 14 +++++++- library/axi_ad9625/axi_ad9625.v | 17 +++++++++- library/axi_ad9671/axi_ad9671.v | 20 +++++++++++- library/axi_ad9684/axi_ad9684.v | 17 +++++++++- library/axi_ad9963/axi_ad9963_rx.v | 14 +++++++- library/axi_adaq8092/axi_adaq8092.v | 6 ++++ library/axi_adrv9001/axi_adrv9001_rx.v | 12 ++++++- library/axi_generic_adc/axi_generic_adc.v | 15 +++++++++ library/axi_ltc2387/axi_ltc2387.v | 5 +++ .../ad_ip_jesd204_tpl_adc_regmap.v | 5 +++ 16 files changed, 205 insertions(+), 9 deletions(-) diff --git a/docs/regmap/adi_regmap_adc.txt b/docs/regmap/adi_regmap_adc.txt index faeb15659..6d3bd47ce 100644 --- a/docs/regmap/adi_regmap_adc.txt +++ b/docs/regmap/adi_regmap_adc.txt @@ -436,6 +436,38 @@ ENDFIELD ############################################################################################ ############################################################################################ +REG +0x0020 +REG_ADC_CUSTOM_WR +ADC Custom Write Data +ENDREG + +FIELD +[31:0] 0x0000 +ADC_CUSTOM_WR[31:0] +RW +Custom write to the ADC available registers. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0X0021 +REG_ADC_CUSTOM_RD +ADC Custom Read Data +ENDREG + +FIELD +[31:0] 0x0000 +ADC_CUSTOM_RD[31:0] +RO +Custom read of the ADC available registers. +ENDFIELD + +############################################################################################ +############################################################################################ + REG 0x0022 REG_UI_STATUS diff --git a/library/axi_ad7768/axi_ad7768.v b/library/axi_ad7768/axi_ad7768.v index b3b71a10e..872973038 100644 --- a/library/axi_ad7768/axi_ad7768.v +++ b/library/axi_ad7768/axi_ad7768.v @@ -311,6 +311,11 @@ module axi_ad7768 #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (NUM_CHANNELS), .up_adc_gpio_in (32'b0), diff --git a/library/axi_ad777x/axi_ad777x.v b/library/axi_ad777x/axi_ad777x.v index 99c617793..da2e2233f 100644 --- a/library/axi_ad777x/axi_ad777x.v +++ b/library/axi_ad777x/axi_ad777x.v @@ -307,6 +307,11 @@ module axi_ad777x #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8), .up_adc_gpio_in (32'b0), diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v index 7ed89302e..2784035c1 100644 --- a/library/axi_ad9265/axi_ad9265.v +++ b/library/axi_ad9265/axi_ad9265.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -256,9 +256,19 @@ module axi_ad9265 #( .adc_start_code (), .adc_sref_sync (), .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), .up_pps_rcounter(32'd0), .up_pps_status(1'd0), .up_pps_irq_mask(), + .up_adc_r1_mode (), .up_adc_ce (), .up_status_pn_err (up_status_pn_err), .up_status_pn_oos (up_status_pn_oos), @@ -270,6 +280,11 @@ module axi_ad9265 #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd0), .up_adc_gpio_in (32'd0), diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index f7554bd05..118e015c6 100644 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -32,7 +32,6 @@ // // *************************************************************************** // *************************************************************************** -// ADC channel-need to work on dual mode for pn sequence `timescale 1ns/100ps @@ -362,8 +361,15 @@ module axi_ad9361_rx #( .adc_start_code (), .adc_sref_sync (), .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), .up_adc_ce (), .up_pps_rcounter (up_pps_rcounter), .up_pps_status (up_pps_status), @@ -379,6 +385,11 @@ module axi_ad9361_rx #( .up_drp_rdata (up_drp_rdata), .up_drp_ready (up_drp_ready), .up_drp_locked (up_drp_locked), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd3), .up_adc_gpio_in (up_adc_gpio_in), diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v index 1afd20386..404080ba1 100644 --- a/library/axi_ad9434/axi_ad9434_core.v +++ b/library/axi_ad9434/axi_ad9434_core.v @@ -178,9 +178,19 @@ module axi_ad9434_core #( .adc_clk_ratio (32'd4), .adc_start_code (), .adc_sref_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), .adc_sync (), .up_pps_rcounter(32'h0), + .up_adc_r1_mode (), .up_pps_status(1'b0), .up_pps_irq_mask(), @@ -192,6 +202,11 @@ module axi_ad9434_core #( .up_drp_sel (up_drp_sel), .up_drp_wr (up_drp_wr), .up_drp_addr (up_drp_addr), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_drp_wdata (up_drp_wdata), .up_drp_rdata (up_drp_rdata), .up_drp_ready (up_drp_ready), diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index f82021ddd..4a2d23a26 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -247,8 +247,15 @@ module axi_ad9467#( .adc_start_code (), .adc_sref_sync (), .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), .up_pps_rcounter (32'd0), .up_pps_status (1'd0), .up_pps_irq_mask (), @@ -264,6 +271,11 @@ module axi_ad9467#( .up_drp_rdata (16'b0), .up_drp_ready (1'b0), .up_drp_locked (1'b1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd1), .up_adc_gpio_in (32'd0), diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index 53f6be507..d93803d0e 100644 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -211,9 +211,19 @@ module axi_ad9625 #( .adc_start_code (), .adc_sync (), .adc_sref_sync (adc_sref_sync_s), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), .up_pps_rcounter(32'h0), .up_pps_status(1'b0), .up_pps_irq_mask(), + .up_adc_r1_mode (), .up_adc_ce (), .up_status_pn_err (up_adc_pn_err_s), .up_status_pn_oos (up_adc_pn_oos_s), @@ -225,6 +235,11 @@ module axi_ad9625 #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd1), .up_adc_gpio_in (32'd0), diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index fb6e8c5d8..370ea62c1 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -247,6 +247,19 @@ module axi_ad9671 #( .adc_start_code (adc_start_code), .adc_sref_sync (), .adc_sync (adc_sync), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter ('d0), + .up_pps_status ('d0), + .up_pps_irq_mask (), + .up_adc_r1_mode (), .up_adc_ce (), .up_status_pn_err (up_status_pn_err), .up_status_pn_oos (up_status_pn_oos), @@ -258,6 +271,11 @@ module axi_ad9671 #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd7), .up_adc_gpio_in (32'd0), diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v index b36339dce..9a801a042 100644 --- a/library/axi_ad9684/axi_ad9684.v +++ b/library/axi_ad9684/axi_ad9684.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -233,9 +233,19 @@ module axi_ad9684 #( .adc_start_code (), .adc_sref_sync(), .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), .up_pps_rcounter(32'd0), .up_pps_status(1'd0), .up_pps_irq_mask(), + .up_adc_r1_mode (), .up_adc_ce(), .up_status_pn_err (up_status_pn_err_s), .up_status_pn_oos (up_status_pn_oos_s), @@ -247,6 +257,11 @@ module axi_ad9684 #( .up_drp_rdata (up_drp_rdata_s), .up_drp_ready (up_drp_ready_s), .up_drp_locked (up_drp_locked_s), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd1), .up_adc_gpio_in (32'd0), diff --git a/library/axi_ad9963/axi_ad9963_rx.v b/library/axi_ad9963/axi_ad9963_rx.v index 5840ef0da..82837dfb0 100644 --- a/library/axi_ad9963/axi_ad9963_rx.v +++ b/library/axi_ad9963/axi_ad9963_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -239,8 +239,15 @@ module axi_ad9963_rx #( .adc_start_code (), .adc_sref_sync (), .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), .up_pps_rcounter(32'h0), .up_pps_status(1'b0), .up_pps_irq_mask(), @@ -256,6 +263,11 @@ module axi_ad9963_rx #( .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax_out (), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_in (8'd1), .up_adc_gpio_in (32'h0), .up_adc_gpio_out (), diff --git a/library/axi_adaq8092/axi_adaq8092.v b/library/axi_adaq8092/axi_adaq8092.v index d811185da..498d808f5 100644 --- a/library/axi_adaq8092/axi_adaq8092.v +++ b/library/axi_adaq8092/axi_adaq8092.v @@ -314,6 +314,7 @@ module axi_adaq8092 #( .adc_ext_sync_arm(), .adc_ext_sync_disarm(), .adc_ext_sync_manual_req(), + .adc_crc_enable (), .adc_num_lanes(), .adc_symb_op(), .adc_symb_8_16b(), @@ -332,6 +333,11 @@ module axi_adaq8092 #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd0), .up_adc_gpio_in (32'd0), diff --git a/library/axi_adrv9001/axi_adrv9001_rx.v b/library/axi_adrv9001/axi_adrv9001_rx.v index 6b329243a..d4d4921ec 100644 --- a/library/axi_adrv9001/axi_adrv9001_rx.v +++ b/library/axi_adrv9001/axi_adrv9001_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -366,7 +366,12 @@ module axi_adrv9001_rx #( .adc_start_code (), .adc_sref_sync (), .adc_sync (adc_sync), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), .adc_num_lanes (adc_num_lanes), + .adc_custom_control (), + .adc_crc_enable (), .adc_sdr_ddr_n (adc_sdr_ddr_n), .adc_symb_op (adc_symb_op), .adc_symb_8_16b (adc_symb_8_16b), @@ -385,6 +390,11 @@ module axi_adrv9001_rx #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd3), .up_adc_gpio_in (32'd0), diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v index 065408b2e..5d66b7e3d 100644 --- a/library/axi_generic_adc/axi_generic_adc.v +++ b/library/axi_generic_adc/axi_generic_adc.v @@ -134,9 +134,19 @@ module axi_generic_adc #( .adc_start_code (), .adc_sref_sync (), .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), .up_pps_rcounter (32'b0), .up_pps_status (1'b0), .up_pps_irq_mask (), + .up_adc_r1_mode (), .up_adc_ce (), .up_status_pn_err (1'b0), .up_status_pn_oos (1'b0), @@ -148,6 +158,11 @@ module axi_generic_adc #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (NUM_OF_CHANNELS), .up_adc_gpio_in (32'b0), diff --git a/library/axi_ltc2387/axi_ltc2387.v b/library/axi_ltc2387/axi_ltc2387.v index 0dc8e6fd7..30c764bcc 100644 --- a/library/axi_ltc2387/axi_ltc2387.v +++ b/library/axi_ltc2387/axi_ltc2387.v @@ -287,6 +287,11 @@ module axi_ltc2387 #( .up_drp_rdata (32'b0), .up_drp_ready (1'b0), .up_drp_locked (1'b1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (8'd1), .up_adc_gpio_in (32'd0), diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v index 125a11bff..7958504c6 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -242,6 +242,11 @@ module ad_ip_jesd204_tpl_adc_regmap #( .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), + .adc_custom_wr (), + .adc_write_req (), + .adc_custom_rd ('d0), + .adc_read_valid ('d0), + .adc_read_req (), .up_usr_chanmax_out (), .up_usr_chanmax_in (NUM_CHANNELS), .up_adc_gpio_in (32'd0),