From 28c06d505f202df1d1c99dda5db3c4db78f234db Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Thu, 6 Jul 2023 16:54:40 +0300 Subject: [PATCH] Add/edit copyright and license for .v, .sv files Signed-off-by: Iulia Moldovan --- .../ad463x_data_capture/ad463x_data_capture.v | 2 +- library/axi_ad5766/axi_ad5766.v | 2 +- library/axi_ad5766/up_ad5766_sequencer.v | 2 +- library/axi_ad7606x/axi_ad7606x.v | 2 +- library/axi_ad7606x/axi_ad7606x_16b_pif.v | 2 +- library/axi_ad7606x/axi_ad7606x_18b_pif.v | 2 +- library/axi_ad7616/axi_ad7616.v | 2 +- library/axi_ad7616/axi_ad7616_control.v | 2 +- library/axi_ad7616/axi_ad7616_maxis2wrfifo.v | 2 +- library/axi_ad7616/axi_ad7616_pif.v | 2 +- library/axi_ad7768/axi_ad7768.v | 4 +-- library/axi_ad7768/axi_ad7768_if.v | 2 +- library/axi_ad777x/axi_ad777x.v | 4 +-- library/axi_ad777x/axi_ad777x_if.v | 2 +- library/axi_ad9122/axi_ad9122.v | 2 +- library/axi_ad9122/axi_ad9122_channel.v | 2 +- library/axi_ad9122/axi_ad9122_core.v | 2 +- library/axi_ad9122/axi_ad9122_if.v | 2 +- library/axi_ad9250/axi_ad9250.v | 2 +- library/axi_ad9265/axi_ad9265.v | 2 +- library/axi_ad9265/axi_ad9265_channel.v | 2 +- library/axi_ad9265/axi_ad9265_if.v | 2 +- library/axi_ad9265/axi_ad9265_pnmon.v | 2 +- library/axi_ad9361/axi_ad9361.v | 2 +- library/axi_ad9361/axi_ad9361_rx.v | 2 +- library/axi_ad9361/axi_ad9361_rx_channel.v | 2 +- library/axi_ad9361/axi_ad9361_rx_pnmon.v | 2 +- library/axi_ad9361/axi_ad9361_tdd.v | 2 +- library/axi_ad9361/axi_ad9361_tdd_if.v | 2 +- library/axi_ad9361/axi_ad9361_tx.v | 2 +- library/axi_ad9361/axi_ad9361_tx_channel.v | 2 +- .../axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v | 2 +- .../axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v | 2 +- library/axi_ad9361/intel/axi_ad9361_cmos_if.v | 2 +- library/axi_ad9361/intel/axi_ad9361_lvds_if.v | 2 +- .../axi_ad9361/intel/axi_ad9361_lvds_if_10.v | 2 +- .../axi_ad9361/intel/axi_ad9361_lvds_if_c5.v | 2 +- .../axi_ad9361/xilinx/axi_ad9361_cmos_if.v | 2 +- .../axi_ad9361/xilinx/axi_ad9361_lvds_if.v | 2 +- library/axi_ad9434/axi_ad9434.v | 2 +- library/axi_ad9434/axi_ad9434_core.v | 2 +- library/axi_ad9434/axi_ad9434_if.v | 2 +- library/axi_ad9434/axi_ad9434_pnmon.v | 2 +- library/axi_ad9467/axi_ad9467.v | 2 +- library/axi_ad9467/axi_ad9467_channel.v | 2 +- library/axi_ad9467/axi_ad9467_if.v | 2 +- library/axi_ad9467/axi_ad9467_pnmon.v | 2 +- library/axi_ad9625/axi_ad9625.v | 2 +- library/axi_ad9625/axi_ad9625_channel.v | 2 +- library/axi_ad9625/axi_ad9625_if.v | 2 +- library/axi_ad9625/axi_ad9625_pnmon.v | 2 +- library/axi_ad9671/axi_ad9671.v | 2 +- library/axi_ad9671/axi_ad9671_channel.v | 2 +- library/axi_ad9671/axi_ad9671_if.v | 2 +- library/axi_ad9671/axi_ad9671_pnmon.v | 2 +- library/axi_ad9684/axi_ad9684.v | 2 +- library/axi_ad9684/axi_ad9684_channel.v | 2 +- library/axi_ad9684/axi_ad9684_if.v | 2 +- library/axi_ad9684/axi_ad9684_pnmon.v | 2 +- library/axi_ad9739a/axi_ad9739a.v | 2 +- library/axi_ad9739a/axi_ad9739a_channel.v | 2 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+- library/axi_adc_decimate/fir_decim.v | 2 +- library/axi_adc_trigger/axi_adc_trigger.v | 2 +- library/axi_adc_trigger/axi_adc_trigger_reg.v | 2 +- library/axi_adrv9001/adrv9001_aligner4.v | 2 +- library/axi_adrv9001/adrv9001_aligner8.v | 2 +- library/axi_adrv9001/adrv9001_pack.v | 2 +- library/axi_adrv9001/adrv9001_rx.v | 2 +- library/axi_adrv9001/adrv9001_rx_link.v | 2 +- library/axi_adrv9001/adrv9001_tx.v | 2 +- library/axi_adrv9001/adrv9001_tx_link.v | 2 +- library/axi_adrv9001/axi_adrv9001.v | 2 +- library/axi_adrv9001/axi_adrv9001_core.v | 2 +- library/axi_adrv9001/axi_adrv9001_if.v | 2 +- library/axi_adrv9001/axi_adrv9001_rx.v | 2 +- .../axi_adrv9001/axi_adrv9001_rx_channel.v | 2 +- library/axi_adrv9001/axi_adrv9001_tdd.v | 2 +- library/axi_adrv9001/axi_adrv9001_tx.v | 2 +- .../axi_adrv9001/axi_adrv9001_tx_channel.v | 2 +- library/axi_adrv9001/intel/adrv9001_rx.v | 2 +- library/axi_adrv9001/intel/adrv9001_tx.v | 2 +- library/axi_clkgen/axi_clkgen.v | 2 +- library/axi_clock_monitor/axi_clock_monitor.v | 4 +-- .../axi_dac_interpolate/axi_dac_interpolate.v | 2 +- .../axi_dac_interpolate_filter.v | 2 +- .../axi_dac_interpolate_reg.v | 2 +- library/axi_dmac/address_generator.v | 2 +- library/axi_dmac/axi_dmac.v | 2 +- library/axi_dmac/axi_dmac_burst_memory.v | 2 +- library/axi_dmac/axi_dmac_regmap.v | 2 +- library/axi_dmac/axi_dmac_regmap_request.v | 2 +- library/axi_dmac/axi_dmac_reset_manager.v | 2 +- library/axi_dmac/axi_dmac_resize_dest.v | 2 +- library/axi_dmac/axi_dmac_resize_src.v | 2 +- library/axi_dmac/axi_dmac_response_manager.v | 2 +- library/axi_dmac/axi_dmac_transfer.v | 4 +-- library/axi_dmac/axi_register_slice.v | 2 +- library/axi_dmac/data_mover.v | 2 +- library/axi_dmac/dest_axi_mm.v | 2 +- library/axi_dmac/dest_axi_stream.v | 2 +- library/axi_dmac/dest_fifo_inf.v | 2 +- library/axi_dmac/dmac_2d_transfer.v | 2 +- library/axi_dmac/request_arb.v | 2 +- library/axi_dmac/request_generator.v | 2 +- library/axi_dmac/response_generator.v | 2 +- library/axi_dmac/response_handler.v | 2 +- library/axi_dmac/splitter.v | 2 +- library/axi_dmac/src_axi_mm.v | 2 +- library/axi_dmac/src_axi_stream.v | 2 +- library/axi_dmac/src_fifo_inf.v | 2 +- library/axi_dmac/tb/axi_read_slave.v | 2 +- library/axi_dmac/tb/axi_slave.v | 2 +- library/axi_dmac/tb/axi_write_slave.v | 2 +- library/axi_dmac/tb/dma_read_shutdown_tb.v | 2 +- library/axi_dmac/tb/dma_read_tb.v | 2 +- library/axi_dmac/tb/dma_write_shutdown_tb.v | 2 +- library/axi_dmac/tb/dma_write_tb.v | 2 +- library/axi_dmac/tb/regmap_tb.v | 2 +- library/axi_dmac/tb/reset_manager_tb.v | 2 +- library/axi_dmac/tb/tb_base.v | 2 +- library/axi_fan_control/axi_fan_control.v | 2 +- library/axi_fmcadc5_sync/axi_fmcadc5_sync.v | 2 +- .../axi_fmcadc5_sync_calcor.v | 2 +- library/axi_generic_adc/axi_generic_adc.v | 2 +- library/axi_gpreg/axi_gpreg.v | 2 +- library/axi_gpreg/axi_gpreg_clock_mon.v | 2 +- library/axi_gpreg/axi_gpreg_io.v | 2 +- library/axi_hdmi_rx/axi_hdmi_rx.v | 2 +- library/axi_hdmi_rx/axi_hdmi_rx_core.v | 2 +- library/axi_hdmi_rx/axi_hdmi_rx_es.v | 2 +- library/axi_hdmi_rx/axi_hdmi_rx_tpm.v | 2 +- library/axi_hdmi_tx/axi_hdmi_tx.v | 2 +- library/axi_hdmi_tx/axi_hdmi_tx_core.v | 2 +- library/axi_hdmi_tx/axi_hdmi_tx_es.v | 2 +- library/axi_hdmi_tx/axi_hdmi_tx_vdma.v | 2 +- library/axi_intr_monitor/axi_intr_monitor.v | 2 +- library/axi_laser_driver/axi_laser_driver.v | 2 +- .../axi_laser_driver_regmap.v | 2 +- .../axi_logic_analyzer/axi_logic_analyzer.v | 2 +- .../axi_logic_analyzer_reg.v | 2 +- .../axi_logic_analyzer_trigger.v | 2 +- library/axi_ltc2387/axi_ltc2387.v | 2 +- library/axi_ltc2387/axi_ltc2387_channel.v | 2 +- library/axi_ltc2387/axi_ltc2387_if.v | 2 +- library/axi_pulse_gen/axi_pulse_gen.v | 2 +- library/axi_pulse_gen/axi_pulse_gen_regmap.v | 2 +- library/axi_pwm_gen/axi_pwm_gen.v | 2 +- library/axi_pwm_gen/axi_pwm_gen_1.v | 2 +- library/axi_pwm_gen/axi_pwm_gen_regmap.v | 2 +- .../axi_rd_wr_combiner/axi_rd_wr_combiner.v | 2 +- library/axi_sysid/axi_sysid.v | 2 +- library/axi_tdd/axi_tdd.sv | 2 +- library/axi_tdd/axi_tdd_channel.sv | 2 +- library/axi_tdd/axi_tdd_counter.sv | 2 +- library/axi_tdd/axi_tdd_pkg.sv | 2 +- library/axi_tdd/axi_tdd_regmap.sv | 2 +- library/axi_tdd/axi_tdd_sync_gen.sv | 2 +- .../cn0363_dma_sequencer.v | 2 +- .../cn0363_phase_data_sync.v | 2 +- library/common/ad_3w_spi.v | 2 +- library/common/ad_addsub.v | 2 +- library/common/ad_adl5904_rst.v | 2 +- library/common/ad_axis_inf_rx.v | 2 +- library/common/ad_b2g.v | 2 +- library/common/ad_bus_mux.v | 2 +- library/common/ad_csc.v | 2 +- library/common/ad_csc_CrYCb2RGB.v | 2 +- library/common/ad_csc_RGB2CrYCb.v | 2 +- library/common/ad_datafmt.v | 2 +- library/common/ad_dds.v | 2 +- library/common/ad_dds_1.v | 2 +- library/common/ad_dds_2.v | 2 +- library/common/ad_dds_cordic_pipe.v | 2 +- library/common/ad_dds_sine.v | 2 +- library/common/ad_dds_sine_cordic.v | 2 +- library/common/ad_edge_detect.v | 2 +- library/common/ad_g2b.v | 2 +- library/common/ad_iobuf.v | 2 +- library/common/ad_iqcor.v | 2 +- library/common/ad_mem.v | 2 +- library/common/ad_mem_asym.v | 2 +- library/common/ad_mux.v | 2 +- library/common/ad_mux_core.v | 2 +- library/common/ad_pack.v | 2 +- library/common/ad_perfect_shuffle.v | 2 +- library/common/ad_pngen.v | 32 +++++++++++------ library/common/ad_pnmon.v | 2 +- library/common/ad_pps_receiver.v | 2 +- library/common/ad_rst.v | 2 +- library/common/ad_ss_422to444.v | 2 +- library/common/ad_ss_444to422.v | 2 +- library/common/ad_sysref_gen.v | 2 +- library/common/ad_tdd_control.v | 2 +- library/common/ad_upack.v | 2 +- library/common/ad_xcvr_rx_if.v | 2 +- library/common/tb/ad_mux_tb.v | 35 +++++++++++++++++++ library/common/tb/ad_pack_tb.v | 35 +++++++++++++++++++ library/common/tb/ad_upack_tb.v | 35 +++++++++++++++++++ library/common/up_adc_channel.v | 2 +- library/common/up_adc_common.v | 2 +- library/common/up_axi.v | 2 +- library/common/up_clkgen.v | 2 +- library/common/up_clock_mon.v | 2 +- library/common/up_dac_channel.v | 2 +- library/common/up_dac_common.v | 2 +- library/common/up_delay_cntrl.v | 2 +- library/common/up_hdmi_rx.v | 2 +- library/common/up_hdmi_tx.v | 2 +- library/common/up_pmod.v | 2 +- library/common/up_tdd_cntrl.v | 2 +- library/common/up_xfer_cntrl.v | 2 +- library/common/up_xfer_status.v | 2 +- library/common/util_axis_upscale.v | 2 +- library/common/util_dec256sinc24b.v | 4 +-- library/common/util_delay.v | 2 +- library/common/util_ext_sync.v | 32 +++++++++++------ library/common/util_pulse_gen.v | 2 +- library/cordic_demod/cordic_demod.v | 2 +- library/data_offload/data_offload.v | 2 +- library/data_offload/data_offload_fsm.v | 2 +- library/data_offload/data_offload_regmap.v | 2 +- library/intel/adi_jesd204/adi_jesd204_glue.v | 2 +- library/intel/avl_adxcfg/avl_adxcfg.v | 2 +- .../avl_adxcvr_octet_swap.v | 2 +- library/intel/avl_adxphy/avl_adxphy.v | 2 +- library/intel/avl_dacfifo/avl_dacfifo.v | 2 +- library/intel/avl_dacfifo/avl_dacfifo_rd.v | 2 +- library/intel/avl_dacfifo/avl_dacfifo_wr.v | 2 +- .../intel/avl_dacfifo/util_dacfifo_bypass.v | 2 +- library/intel/axi_adxcvr/axi_adxcvr.v | 2 +- library/intel/axi_adxcvr/axi_adxcvr_up.v | 2 +- library/intel/common/ad_dcfilter.v | 2 +- library/intel/common/ad_mul.v | 2 +- library/intel/jesd204_phy/jesd204_phy_glue.v | 2 +- library/intel/util_clkdiv/util_clkdiv.v | 2 +- .../ad_ip_jesd204_tpl_adc.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_adc_channel.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_adc_core.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_adc_deframer.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_adc_pnmon.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_adc_regmap.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_common/up_tpl_common.v | 2 +- .../ad_ip_jesd204_tpl_dac.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_dac_channel.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_dac_core.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_dac_framer.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_dac_pn.v | 32 +++++++++++------ .../ad_ip_jesd204_tpl_dac_regmap.v | 32 +++++++++++------ .../axi_spi_engine/axi_spi_engine.v | 2 +- .../spi_axis_reorder/spi_axis_reorder.v | 2 +- .../spi_engine_execution.v | 2 +- .../spi_engine_interconnect.v | 2 +- .../spi_engine_offload/spi_engine_offload.v | 2 +- library/sysid_rom/sysid_rom.v | 2 +- library/util_adcfifo/util_adcfifo.v | 2 +- library/util_axis_fifo/util_axis_fifo.v | 2 +- .../util_axis_fifo_address_generator.v | 2 +- .../util_axis_fifo_asym/util_axis_fifo_asym.v | 2 +- library/util_axis_resize/util_axis_resize.v | 2 +- library/util_bsplit/util_bsplit.v | 2 +- library/util_cdc/sync_bits.v | 2 +- library/util_cdc/sync_data.v | 2 +- library/util_cdc/sync_event.v | 2 +- library/util_cdc/sync_gray.v | 2 +- library/util_cic/cic_comb.v | 2 +- library/util_cic/cic_int.v | 2 +- library/util_dacfifo/util_dacfifo.v | 2 +- library/util_dacfifo/util_dacfifo_bypass.v | 2 +- library/util_do_ram/util_do_ram.v | 2 +- library/util_extract/util_extract.v | 2 +- library/util_fir_dec/util_fir_dec.v | 2 +- library/util_fir_int/util_fir_int.v | 2 +- library/util_gmii_to_rgmii/mdc_mdio.v | 2 +- .../util_gmii_to_rgmii/util_gmii_to_rgmii.v | 2 +- library/util_hbm/util_hbm.v | 2 +- library/util_mfifo/util_mfifo.v | 2 +- library/util_mii_to_rmii/mac_phy_link.v | 2 +- library/util_mii_to_rmii/phy_mac_link.v | 2 +- library/util_mii_to_rmii/util_mii_to_rmii.v | 2 +- library/util_pack/tb/cpack_tb.v | 4 +-- library/util_pack/tb/tb_base.v | 4 +-- library/util_pack/tb/underflow_tb.v | 4 +-- library/util_pack/tb/upack_tb.v | 4 +-- library/util_pack/util_cpack2/util_cpack2.v | 4 +-- .../util_pack/util_cpack2/util_cpack2_impl.v | 4 +-- .../util_pack/util_pack_common/pack_ctrl.v | 4 +-- .../util_pack_common/pack_interconnect.v | 4 +-- .../util_pack/util_pack_common/pack_network.v | 4 +-- .../util_pack/util_pack_common/pack_shell.v | 4 +-- library/util_pack/util_upack2/util_upack2.v | 4 +-- .../util_pack/util_upack2/util_upack2_impl.v | 4 +-- library/util_pad/util_pad.v | 32 +++++++++++------ library/util_rfifo/util_rfifo.v | 2 +- .../util_sigma_delta_spi.v | 2 +- library/util_tdd_sync/util_tdd_sync.v | 2 +- library/util_var_fifo/util_var_fifo.v | 2 +- library/util_wfifo/util_wfifo.v | 2 +- library/xilinx/axi_adcfifo/axi_adcfifo.v | 2 +- library/xilinx/axi_adcfifo/axi_adcfifo_adc.v | 2 +- library/xilinx/axi_adcfifo/axi_adcfifo_dma.v | 2 +- library/xilinx/axi_adcfifo/axi_adcfifo_rd.v | 2 +- library/xilinx/axi_adcfifo/axi_adcfifo_wr.v | 2 +- library/xilinx/axi_adxcvr/axi_adxcvr.v | 2 +- library/xilinx/axi_adxcvr/axi_adxcvr_es.v | 2 +- library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v | 2 +- .../xilinx/axi_adxcvr/axi_adxcvr_mstatus.v | 2 +- library/xilinx/axi_adxcvr/axi_adxcvr_up.v | 2 +- library/xilinx/axi_dacfifo/axi_dacfifo.v | 2 +- .../axi_dacfifo/axi_dacfifo_address_buffer.v | 2 +- library/xilinx/axi_dacfifo/axi_dacfifo_rd.v | 2 +- library/xilinx/axi_dacfifo/axi_dacfifo_wr.v | 2 +- library/xilinx/axi_xcvrlb/axi_xcvrlb.v | 2 +- library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v | 2 +- library/xilinx/common/ad_data_clk.v | 2 +- library/xilinx/common/ad_data_in.v | 2 +- library/xilinx/common/ad_data_out.v | 2 +- library/xilinx/common/ad_dcfilter.v | 2 +- library/xilinx/common/ad_mmcm_drp.v | 2 +- library/xilinx/common/ad_mul.v | 2 +- library/xilinx/common/ad_serdes_clk.v | 2 +- library/xilinx/common/ad_serdes_in.v | 2 +- library/xilinx/common/ad_serdes_out.v | 2 +- library/xilinx/util_adxcvr/util_adxcvr.v | 2 +- library/xilinx/util_adxcvr/util_adxcvr_xch.v | 2 +- library/xilinx/util_adxcvr/util_adxcvr_xcm.v | 2 +- library/xilinx/util_clkdiv/util_clkdiv.v | 2 +- projects/ad40xx_fmc/zed/system_top_ad40xx.v | 4 +-- projects/ad40xx_fmc/zed/system_top_adaq400x.v | 4 +-- projects/ad4110/zed/system_top.v | 2 +- projects/ad4134_fmc/zed/system_top.v | 2 +- projects/ad4630_fmc/zed/system_top.v | 4 +-- projects/ad469x_fmc/zed/system_top.v | 4 +-- projects/ad5758_sdz/zed/system_top.v | 4 +-- projects/ad5766_sdz/zed/system_top.v | 2 +- projects/ad6676evb/vc707/system_top.v | 2 +- projects/ad6676evb/zc706/system_top.v | 2 +- projects/ad7134_fmc/zed/system_top.v | 2 +- projects/ad719x_asdz/coraz7s/system_top.v | 4 +-- projects/ad738x_fmc/zed/system_top.v | 2 +- .../ad7405_fmc/zed/system_top_differential.v | 4 +-- .../ad7405_fmc/zed/system_top_singlended.v | 4 +-- projects/ad7606x_fmc/zed/system_top.v | 2 +- projects/ad7616_sdz/zc706/system_top_pi.v | 2 +- projects/ad7616_sdz/zc706/system_top_si.v | 2 +- projects/ad7616_sdz/zed/system_top_pi.v | 2 +- projects/ad7616_sdz/zed/system_top_si.v | 2 +- projects/ad77681evb/zed/system_top.v | 2 +- projects/ad7768evb/zed/system_top.v | 2 +- projects/ad777x_ardz/de10nano/system_top.v | 4 +-- projects/ad777x_ardz/zed/system_top.v | 2 +- projects/ad9081_fmca_ebz/a10soc/system_top.v | 2 +- projects/ad9081_fmca_ebz/vck190/system_top.v | 2 +- projects/ad9081_fmca_ebz/vcu118/system_top.v | 2 +- projects/ad9081_fmca_ebz/vcu128/system_top.v | 2 +- projects/ad9081_fmca_ebz/zc706/system_top.v | 2 +- projects/ad9081_fmca_ebz/zcu102/system_top.v | 2 +- .../zcu102/system_top.v | 2 +- projects/ad9083_evb/a10soc/system_top.v | 2 +- projects/ad9083_evb/zcu102/system_top.v | 2 +- projects/ad9083_vna/zcu102/system_top.v | 2 +- projects/ad9208_dual_ebz/vcu118/system_top.v | 2 +- projects/ad9209_fmca_ebz/vck190/system_top.v | 2 +- projects/ad9213_dual_ebz/s10soc/system_top.v | 2 +- projects/ad9265_fmc/common/ad9265_spi.v | 2 +- projects/ad9265_fmc/zc706/system_top.v | 2 +- projects/ad9434_fmc/common/ad9434_spi.v | 2 +- projects/ad9434_fmc/zc706/system_top.v | 2 +- projects/ad9467_fmc/common/ad9467_spi.v | 2 +- projects/ad9467_fmc/kc705/system_top.v | 2 +- projects/ad9467_fmc/zed/system_top.v | 2 +- projects/ad9656_fmc/zcu102/system_top.v | 2 +- projects/ad9695_fmc/zcu102/system_top.v | 2 +- projects/ad9739a_fmc/zc706/system_top.v | 2 +- projects/ad9783_ebz/zcu102/system_top.v | 2 +- projects/ad_fmclidar1_ebz/a10soc/system_top.v | 2 +- .../common/util_axis_syncgen.v | 2 +- .../ad_fmclidar1_ebz/common/util_tia_chsel.v | 2 +- projects/ad_fmclidar1_ebz/zc706/system_top.v | 2 +- projects/ad_fmclidar1_ebz/zcu102/system_top.v | 2 +- .../common/quad_mxfe_gpio_mux.v | 2 +- projects/ad_quadmxfe1_ebz/vcu118/system_top.v | 2 +- projects/adaq7980_sdz/zed/system_top.v | 2 +- projects/adaq8092_fmc/zed/system_top.v | 2 +- projects/adrv9001/a10soc/system_top.v | 2 +- projects/adrv9001/zc706/system_top.v | 2 +- projects/adrv9001/zcu102/system_top.v | 2 +- projects/adrv9001/zed/system_top.v | 2 +- projects/adrv9009/a10soc/system_top.v | 2 +- projects/adrv9009/s10soc/system_top.v | 2 +- projects/adrv9009/zc706/system_top.v | 2 +- projects/adrv9009/zcu102/system_top.v | 2 +- .../adrv9009zu11eg/adrv2crr_fmc/system_top.v | 4 +-- .../adrv2crr_fmcomms8/system_top.v | 4 +-- .../adrv2crr_fmcxmwbr1/system_top.v | 4 +-- .../adrv2crr_xmicrowave/system_top.v | 4 +-- .../common/adrv9009zu11eg_spi.v | 2 +- .../adrv9361z7035/ccbob_cmos/system_top.v | 2 +- .../adrv9361z7035/ccbob_lvds/system_top.v | 2 +- .../adrv9361z7035/ccfmc_lvds/system_top.v | 2 +- .../adrv9361z7035/ccpackrf_lvds/system_top.v | 2 +- .../adrv9364z7020/ccbob_cmos/system_top.v | 2 +- .../adrv9364z7020/ccbob_lvds/system_top.v | 2 +- .../adrv9364z7020/ccpackrf_lvds/system_top.v | 2 +- projects/adrv9371x/a10soc/system_top.v | 2 +- projects/adrv9371x/kcu105/system_top.v | 2 +- projects/adrv9371x/zc706/system_top.v | 2 +- projects/adrv9371x/zcu102/system_top.v | 2 +- projects/adv7511/zc702/system_top.v | 2 +- projects/adv7511/zc706/system_top.v | 2 +- projects/adv7511/zed/system_top.v | 2 +- projects/adv7513/de10nano/system_top.v | 4 +-- projects/arradio/c5soc/system_top.v | 2 +- projects/cn0363/zed/system_top.v | 2 +- projects/cn0501/coraz7s/system_top.v | 2 +- projects/cn0506/a10soc/system_top.v | 2 +- projects/cn0506/zc706/system_top_mii.v | 2 +- projects/cn0506/zc706/system_top_rgmii.v | 2 +- projects/cn0506/zc706/system_top_rmii.v | 2 +- projects/cn0506/zcu102/system_top_mii.v | 2 +- projects/cn0506/zcu102/system_top_rgmii.v | 2 +- projects/cn0506/zcu102/system_top_rmii.v | 2 +- projects/cn0506/zed/system_top_mii.v | 2 +- projects/cn0506/zed/system_top_rgmii.v | 2 +- projects/cn0506/zed/system_top_rmii.v | 2 +- projects/cn0540/coraz7s/system_top.v | 2 +- projects/cn0540/de10nano/system_top.v | 2 +- projects/cn0561/coraz7s/system_top.v | 2 +- projects/cn0561/de10nano/system_top.v | 2 +- projects/cn0561/zed/system_top.v | 2 +- projects/cn0577/zed/system_top.v | 2 +- projects/cn0579/coraz7s/system_top.v | 2 +- projects/cn0579/de10nano/system_top.v | 4 +-- projects/common/a10gx/system_top.v | 2 +- projects/common/a10soc/system_top.v | 2 +- projects/common/ac701/system_top.v | 2 +- projects/common/c5soc/system_top.v | 2 +- projects/common/coraz7s/system_top.v | 4 +-- projects/common/de10nano/system_top.v | 4 +-- projects/common/kc705/system_top.v | 2 +- projects/common/kcu105/system_top.v | 2 +- projects/common/kv260/system_top.v | 2 +- projects/common/s10soc/system_top.v | 2 +- projects/common/vc707/system_top.v | 2 +- projects/common/vc709/system_top.v | 2 +- projects/common/vck190/system_top.v | 2 +- projects/common/vcu118/system_top.v | 2 +- projects/common/vcu128/system_top.v | 2 +- projects/common/vmk180/system_top.v | 2 +- projects/common/zc702/system_top.v | 2 +- projects/common/zc706/system_top.v | 2 +- projects/common/zcu102/system_top.v | 2 +- projects/common/zed/system_top.v | 2 +- projects/dac_fmc_ebz/a10soc/system_top.v | 2 +- projects/dac_fmc_ebz/vcu118/system_top.v | 2 +- projects/dac_fmc_ebz/zc706/system_top.v | 2 +- projects/dac_fmc_ebz/zcu102/system_top.v | 2 +- projects/daq2/a10soc/system_top.v | 2 +- projects/daq2/common/daq2_spi.v | 2 +- projects/daq2/kc705/system_top.v | 2 +- projects/daq2/kcu105/system_top.v | 2 +- projects/daq2/zc706/system_top.v | 2 +- projects/daq2/zcu102/system_top.v | 2 +- projects/daq3/common/daq3_spi.v | 2 +- projects/daq3/kcu105/system_top.v | 2 +- projects/daq3/vcu118/system_top.v | 2 +- projects/daq3/zc706/system_top.v | 2 +- projects/daq3/zcu102/system_top.v | 2 +- projects/fmcadc2/common/fmcadc2_spi.v | 2 +- projects/fmcadc2/vc707/system_top.v | 2 +- projects/fmcadc2/zc706/system_top.v | 2 +- projects/fmcadc5/common/fmcadc5_spi.v | 2 +- projects/fmcadc5/vc707/system_top.v | 2 +- projects/fmcjesdadc1/common/fmcjesdadc1_spi.v | 2 +- projects/fmcjesdadc1/kc705/system_top.v | 2 +- projects/fmcjesdadc1/vc707/system_top.v | 2 +- projects/fmcjesdadc1/zc706/system_top.v | 2 +- projects/fmcomms11/common/fmcomms11_spi.v | 2 +- projects/fmcomms11/zc706/system_top.v | 2 +- projects/fmcomms2/kc705/system_top.v | 2 +- projects/fmcomms2/kcu105/system_top.v | 2 +- projects/fmcomms2/vc707/system_top.v | 2 +- projects/fmcomms2/zc702/system_top.v | 2 +- projects/fmcomms2/zc706/system_top.v | 2 +- projects/fmcomms2/zcu102/system_top.v | 2 +- projects/fmcomms2/zed/system_top.v | 2 +- projects/fmcomms5/zc702/system_top.v | 2 +- projects/fmcomms5/zc706/system_top.v | 2 +- projects/fmcomms5/zcu102/system_top.v | 2 +- projects/fmcomms8/a10soc/system_top.v | 2 +- projects/fmcomms8/common/fmcomms8_spi.v | 2 +- projects/fmcomms8/zcu102/system_top.v | 2 +- projects/imageon/zed/system_top.v | 2 +- projects/jupiter_sdr/system_top.v | 2 +- projects/m2k/common/m2k_spi.v | 2 +- projects/m2k/standalone/system_top.v | 2 +- projects/pluto/system_top.v | 2 +- projects/pulsar_adc_pmdz/coraz7s/system_top.v | 4 +-- projects/sidekiqz2/system_top.v | 2 +- projects/usrpe31x/system_top.v | 2 +- 521 files changed, 973 insertions(+), 688 deletions(-) diff --git a/library/ad463x_data_capture/ad463x_data_capture.v b/library/ad463x_data_capture/ad463x_data_capture.v index 72191ddb0..066c3355a 100644 --- a/library/ad463x_data_capture/ad463x_data_capture.v +++ b/library/ad463x_data_capture/ad463x_data_capture.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad5766/axi_ad5766.v b/library/axi_ad5766/axi_ad5766.v index 652ca347d..a3abaf4d6 100644 --- a/library/axi_ad5766/axi_ad5766.v +++ b/library/axi_ad5766/axi_ad5766.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad5766/up_ad5766_sequencer.v b/library/axi_ad5766/up_ad5766_sequencer.v index 4fef14560..a9ccb7e09 100644 --- a/library/axi_ad5766/up_ad5766_sequencer.v +++ b/library/axi_ad5766/up_ad5766_sequencer.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad7606x/axi_ad7606x.v b/library/axi_ad7606x/axi_ad7606x.v index 9977d31db..91968ff21 100644 --- a/library/axi_ad7606x/axi_ad7606x.v +++ b/library/axi_ad7606x/axi_ad7606x.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad7606x/axi_ad7606x_16b_pif.v b/library/axi_ad7606x/axi_ad7606x_16b_pif.v index f918a3dc9..68bac64e1 100644 --- a/library/axi_ad7606x/axi_ad7606x_16b_pif.v +++ b/library/axi_ad7606x/axi_ad7606x_16b_pif.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad7606x/axi_ad7606x_18b_pif.v b/library/axi_ad7606x/axi_ad7606x_18b_pif.v index 0e1f02c58..fc599bd13 100644 --- a/library/axi_ad7606x/axi_ad7606x_18b_pif.v +++ b/library/axi_ad7606x/axi_ad7606x_18b_pif.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v index 6bd2c1ad0..aa11eb91e 100644 --- a/library/axi_ad7616/axi_ad7616.v +++ b/library/axi_ad7616/axi_ad7616.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v index c2d87e997..4923fc5f4 100644 --- a/library/axi_ad7616/axi_ad7616_control.v +++ b/library/axi_ad7616/axi_ad7616_control.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v index 7e091d143..6db5dbef1 100644 --- a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v +++ b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v index f84d7d144..7e131db05 100644 --- a/library/axi_ad7616/axi_ad7616_pif.v +++ b/library/axi_ad7616/axi_ad7616_pif.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad7768/axi_ad7768.v b/library/axi_ad7768/axi_ad7768.v index 11b1bc88e..0e27f0d55 100644 --- a/library/axi_ad7768/axi_ad7768.v +++ b/library/axi_ad7768/axi_ad7768.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/axi_ad7768/axi_ad7768_if.v b/library/axi_ad7768/axi_ad7768_if.v index eb159f625..a59c898ce 100644 --- a/library/axi_ad7768/axi_ad7768_if.v +++ b/library/axi_ad7768/axi_ad7768_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad777x/axi_ad777x.v b/library/axi_ad777x/axi_ad777x.v index 24ee1decb..d8f1d46eb 100644 --- a/library/axi_ad777x/axi_ad777x.v +++ b/library/axi_ad777x/axi_ad777x.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/axi_ad777x/axi_ad777x_if.v b/library/axi_ad777x/axi_ad777x_if.v index 08c28137c..c260b82e8 100644 --- a/library/axi_ad777x/axi_ad777x_if.v +++ b/library/axi_ad777x/axi_ad777x_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v index 4a479ea42..14952afe5 100644 --- a/library/axi_ad9122/axi_ad9122.v +++ b/library/axi_ad9122/axi_ad9122.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v index 622b6f753..7fecc6765 100644 --- a/library/axi_ad9122/axi_ad9122_channel.v +++ b/library/axi_ad9122/axi_ad9122_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v index 951a59480..5be766ae5 100644 --- a/library/axi_ad9122/axi_ad9122_core.v +++ b/library/axi_ad9122/axi_ad9122_core.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v index 27a186a03..4f9ba61d5 100644 --- a/library/axi_ad9122/axi_ad9122_if.v +++ b/library/axi_ad9122/axi_ad9122_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index 5f83637fb..7c8f1e0eb 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v index 36318def3..92b5b1644 100644 --- a/library/axi_ad9265/axi_ad9265.v +++ b/library/axi_ad9265/axi_ad9265.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9265/axi_ad9265_channel.v b/library/axi_ad9265/axi_ad9265_channel.v index ed5d5f2fe..9eb736fe2 100644 --- a/library/axi_ad9265/axi_ad9265_channel.v +++ b/library/axi_ad9265/axi_ad9265_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9265/axi_ad9265_if.v b/library/axi_ad9265/axi_ad9265_if.v index bdb6735ac..abeb2c74e 100644 --- a/library/axi_ad9265/axi_ad9265_if.v +++ b/library/axi_ad9265/axi_ad9265_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9265/axi_ad9265_pnmon.v b/library/axi_ad9265/axi_ad9265_pnmon.v index a57b3195a..3b51442ce 100644 --- a/library/axi_ad9265/axi_ad9265_pnmon.v +++ b/library/axi_ad9265/axi_ad9265_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 4066c5149..d5e3e0a41 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index ec54bad4e..0e94f63cb 100644 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/axi_ad9361_rx_channel.v b/library/axi_ad9361/axi_ad9361_rx_channel.v index 3e645856a..4ed32492d 100644 --- a/library/axi_ad9361/axi_ad9361_rx_channel.v +++ b/library/axi_ad9361/axi_ad9361_rx_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/axi_ad9361_rx_pnmon.v b/library/axi_ad9361/axi_ad9361_rx_pnmon.v index 393dff5c3..fb90cd859 100644 --- a/library/axi_ad9361/axi_ad9361_rx_pnmon.v +++ b/library/axi_ad9361/axi_ad9361_rx_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v index d1ae5b271..6392bdf25 100644 --- a/library/axi_ad9361/axi_ad9361_tdd.v +++ b/library/axi_ad9361/axi_ad9361_tdd.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/axi_ad9361_tdd_if.v b/library/axi_ad9361/axi_ad9361_tdd_if.v index 7cfe46d8c..3583ceb1e 100644 --- a/library/axi_ad9361/axi_ad9361_tdd_if.v +++ b/library/axi_ad9361/axi_ad9361_tdd_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index e33acbbc6..592b541bd 100644 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v index f66c2af42..417308d7f 100644 --- a/library/axi_ad9361/axi_ad9361_tx_channel.v +++ b/library/axi_ad9361/axi_ad9361_tx_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v b/library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v index 01b3cdff1..a73f6a745 100644 --- a/library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v +++ b/library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v b/library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v index 5a8aa3a78..eebb11fbb 100644 --- a/library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v +++ b/library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/intel/axi_ad9361_cmos_if.v b/library/axi_ad9361/intel/axi_ad9361_cmos_if.v index 138eba27d..a3b02fa10 100644 --- a/library/axi_ad9361/intel/axi_ad9361_cmos_if.v +++ b/library/axi_ad9361/intel/axi_ad9361_cmos_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if.v index 68d494d17..78eb16fdd 100644 --- a/library/axi_ad9361/intel/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/intel/axi_ad9361_lvds_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v index b546f3da9..1e35d1294 100644 --- a/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v +++ b/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v index 8af649fe6..a01980adb 100644 --- a/library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v +++ b/library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v index e7a5cac4e..9e9f47b99 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v index ec772f6cc..ee5ca7ce5 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v index 9623a96f4..cb3da79ac 100644 --- a/library/axi_ad9434/axi_ad9434.v +++ b/library/axi_ad9434/axi_ad9434.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v index 4a8aac8ce..7132f74e7 100644 --- a/library/axi_ad9434/axi_ad9434_core.v +++ b/library/axi_ad9434/axi_ad9434_core.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v index 67e858ed5..b27e59905 100644 --- a/library/axi_ad9434/axi_ad9434_if.v +++ b/library/axi_ad9434/axi_ad9434_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9434/axi_ad9434_pnmon.v b/library/axi_ad9434/axi_ad9434_pnmon.v index 2fcbaac2b..a7c645d0a 100644 --- a/library/axi_ad9434/axi_ad9434_pnmon.v +++ b/library/axi_ad9434/axi_ad9434_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index 60c02eaff..b6dc9bfd9 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9467/axi_ad9467_channel.v b/library/axi_ad9467/axi_ad9467_channel.v index 46771daad..a64d8f66e 100644 --- a/library/axi_ad9467/axi_ad9467_channel.v +++ b/library/axi_ad9467/axi_ad9467_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9467/axi_ad9467_if.v b/library/axi_ad9467/axi_ad9467_if.v index b370abcbb..b804b4640 100644 --- a/library/axi_ad9467/axi_ad9467_if.v +++ b/library/axi_ad9467/axi_ad9467_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9467/axi_ad9467_pnmon.v b/library/axi_ad9467/axi_ad9467_pnmon.v index ecb39d317..8f0ec7934 100644 --- a/library/axi_ad9467/axi_ad9467_pnmon.v +++ b/library/axi_ad9467/axi_ad9467_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index 1d431e014..7aee80700 100644 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9625/axi_ad9625_channel.v b/library/axi_ad9625/axi_ad9625_channel.v index 81a554105..cd6921b57 100644 --- a/library/axi_ad9625/axi_ad9625_channel.v +++ b/library/axi_ad9625/axi_ad9625_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9625/axi_ad9625_if.v b/library/axi_ad9625/axi_ad9625_if.v index 49de21a7b..0ccf1e39c 100644 --- a/library/axi_ad9625/axi_ad9625_if.v +++ b/library/axi_ad9625/axi_ad9625_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9625/axi_ad9625_pnmon.v b/library/axi_ad9625/axi_ad9625_pnmon.v index fcd2b1327..3ffeb058f 100644 --- a/library/axi_ad9625/axi_ad9625_pnmon.v +++ b/library/axi_ad9625/axi_ad9625_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index bb43ae5aa..1872d7a30 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9671/axi_ad9671_channel.v b/library/axi_ad9671/axi_ad9671_channel.v index 2a616dd04..5ecb0c0d4 100644 --- a/library/axi_ad9671/axi_ad9671_channel.v +++ b/library/axi_ad9671/axi_ad9671_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v index d3d5a64aa..7644f3397 100644 --- a/library/axi_ad9671/axi_ad9671_if.v +++ b/library/axi_ad9671/axi_ad9671_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9671/axi_ad9671_pnmon.v b/library/axi_ad9671/axi_ad9671_pnmon.v index b67f09553..6132b787a 100644 --- a/library/axi_ad9671/axi_ad9671_pnmon.v +++ b/library/axi_ad9671/axi_ad9671_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v index 3f70f5710..ce9ac84af 100644 --- a/library/axi_ad9684/axi_ad9684.v +++ b/library/axi_ad9684/axi_ad9684.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9684/axi_ad9684_channel.v b/library/axi_ad9684/axi_ad9684_channel.v index 391ce151b..c6d876887 100644 --- a/library/axi_ad9684/axi_ad9684_channel.v +++ b/library/axi_ad9684/axi_ad9684_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v index 31737ac98..411968073 100644 --- a/library/axi_ad9684/axi_ad9684_if.v +++ b/library/axi_ad9684/axi_ad9684_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9684/axi_ad9684_pnmon.v b/library/axi_ad9684/axi_ad9684_pnmon.v index 6934e3d40..ba0c54004 100644 --- a/library/axi_ad9684/axi_ad9684_pnmon.v +++ b/library/axi_ad9684/axi_ad9684_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9739a/axi_ad9739a.v b/library/axi_ad9739a/axi_ad9739a.v index 1de09e42b..0036a9d2f 100644 --- a/library/axi_ad9739a/axi_ad9739a.v +++ b/library/axi_ad9739a/axi_ad9739a.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9739a/axi_ad9739a_channel.v b/library/axi_ad9739a/axi_ad9739a_channel.v index 1f9ee7da9..925b942f9 100644 --- a/library/axi_ad9739a/axi_ad9739a_channel.v +++ b/library/axi_ad9739a/axi_ad9739a_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v index e0f4bb505..6ab99833c 100644 --- a/library/axi_ad9739a/axi_ad9739a_core.v +++ b/library/axi_ad9739a/axi_ad9739a_core.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v index 0db33caef..c05c5132f 100644 --- a/library/axi_ad9739a/axi_ad9739a_if.v +++ b/library/axi_ad9739a/axi_ad9739a_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9783/axi_ad9783.v b/library/axi_ad9783/axi_ad9783.v index 762257eb3..b11d66dc3 100755 --- a/library/axi_ad9783/axi_ad9783.v +++ b/library/axi_ad9783/axi_ad9783.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9783/axi_ad9783_channel.v b/library/axi_ad9783/axi_ad9783_channel.v index 222d5956c..f96a11d28 100755 --- a/library/axi_ad9783/axi_ad9783_channel.v +++ b/library/axi_ad9783/axi_ad9783_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9783/axi_ad9783_core.v b/library/axi_ad9783/axi_ad9783_core.v index 81e901ec1..3f99661ff 100755 --- a/library/axi_ad9783/axi_ad9783_core.v +++ b/library/axi_ad9783/axi_ad9783_core.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9783/axi_ad9783_if.v b/library/axi_ad9783/axi_ad9783_if.v index f12e85958..b63854445 100755 --- a/library/axi_ad9783/axi_ad9783_if.v +++ b/library/axi_ad9783/axi_ad9783_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9963/axi_ad9963.v b/library/axi_ad9963/axi_ad9963.v index 93655c15e..0ed6b77e0 100644 --- a/library/axi_ad9963/axi_ad9963.v +++ b/library/axi_ad9963/axi_ad9963.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v index 7c71bb103..145f2aa2e 100644 --- a/library/axi_ad9963/axi_ad9963_if.v +++ b/library/axi_ad9963/axi_ad9963_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9963/axi_ad9963_rx.v b/library/axi_ad9963/axi_ad9963_rx.v index f04cdfcc9..3fe3ecb5d 100644 --- a/library/axi_ad9963/axi_ad9963_rx.v +++ b/library/axi_ad9963/axi_ad9963_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9963/axi_ad9963_rx_channel.v b/library/axi_ad9963/axi_ad9963_rx_channel.v index ee47a926d..571056a6e 100644 --- a/library/axi_ad9963/axi_ad9963_rx_channel.v +++ b/library/axi_ad9963/axi_ad9963_rx_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9963/axi_ad9963_rx_pnmon.v b/library/axi_ad9963/axi_ad9963_rx_pnmon.v index 0bb66becd..ec2f4063c 100644 --- a/library/axi_ad9963/axi_ad9963_rx_pnmon.v +++ b/library/axi_ad9963/axi_ad9963_rx_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9963/axi_ad9963_tx.v b/library/axi_ad9963/axi_ad9963_tx.v index 490475392..36b7e421f 100644 --- a/library/axi_ad9963/axi_ad9963_tx.v +++ b/library/axi_ad9963/axi_ad9963_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9963/axi_ad9963_tx_channel.v b/library/axi_ad9963/axi_ad9963_tx_channel.v index 17081973f..0db035e37 100644 --- a/library/axi_ad9963/axi_ad9963_tx_channel.v +++ b/library/axi_ad9963/axi_ad9963_tx_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adaq8092/axi_adaq8092.v b/library/axi_adaq8092/axi_adaq8092.v index 95bd78eea..0ee7188f4 100644 --- a/library/axi_adaq8092/axi_adaq8092.v +++ b/library/axi_adaq8092/axi_adaq8092.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adaq8092/axi_adaq8092_apb_decode.v b/library/axi_adaq8092/axi_adaq8092_apb_decode.v index 33f250835..cc763c0db 100644 --- a/library/axi_adaq8092/axi_adaq8092_apb_decode.v +++ b/library/axi_adaq8092/axi_adaq8092_apb_decode.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adaq8092/axi_adaq8092_channel.v b/library/axi_adaq8092/axi_adaq8092_channel.v index 8bff6fc16..ff3d4940d 100644 --- a/library/axi_adaq8092/axi_adaq8092_channel.v +++ b/library/axi_adaq8092/axi_adaq8092_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adaq8092/axi_adaq8092_if.v b/library/axi_adaq8092/axi_adaq8092_if.v index 681cb7d17..17433b502 100644 --- a/library/axi_adaq8092/axi_adaq8092_if.v +++ b/library/axi_adaq8092/axi_adaq8092_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adaq8092/axi_adaq8092_rand_decode.v b/library/axi_adaq8092/axi_adaq8092_rand_decode.v index 3c76c5dc7..e4e112207 100644 --- a/library/axi_adaq8092/axi_adaq8092_rand_decode.v +++ b/library/axi_adaq8092/axi_adaq8092_rand_decode.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adc_decimate/axi_adc_decimate.v b/library/axi_adc_decimate/axi_adc_decimate.v index b2a29b0d1..9c216cb4b 100644 --- a/library/axi_adc_decimate/axi_adc_decimate.v +++ b/library/axi_adc_decimate/axi_adc_decimate.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adc_decimate/axi_adc_decimate_filter.v b/library/axi_adc_decimate/axi_adc_decimate_filter.v index 9cba878c9..4f21caa02 100644 --- a/library/axi_adc_decimate/axi_adc_decimate_filter.v +++ b/library/axi_adc_decimate/axi_adc_decimate_filter.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adc_decimate/axi_adc_decimate_reg.v b/library/axi_adc_decimate/axi_adc_decimate_reg.v index 507b2f6d7..c57cfb55e 100644 --- a/library/axi_adc_decimate/axi_adc_decimate_reg.v +++ b/library/axi_adc_decimate/axi_adc_decimate_reg.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adc_decimate/cic_decim.v b/library/axi_adc_decimate/cic_decim.v index daf847a3e..138660995 100644 --- a/library/axi_adc_decimate/cic_decim.v +++ b/library/axi_adc_decimate/cic_decim.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adc_decimate/fir_decim.v b/library/axi_adc_decimate/fir_decim.v index d4c988dda..7da46732e 100644 --- a/library/axi_adc_decimate/fir_decim.v +++ b/library/axi_adc_decimate/fir_decim.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v index 4a738744a..6d7274a0a 100644 --- a/library/axi_adc_trigger/axi_adc_trigger.v +++ b/library/axi_adc_trigger/axi_adc_trigger.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adc_trigger/axi_adc_trigger_reg.v b/library/axi_adc_trigger/axi_adc_trigger_reg.v index eeb11a966..a6fae39bf 100644 --- a/library/axi_adc_trigger/axi_adc_trigger_reg.v +++ b/library/axi_adc_trigger/axi_adc_trigger_reg.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_aligner4.v b/library/axi_adrv9001/adrv9001_aligner4.v index 515fb33ae..3d43f57aa 100644 --- a/library/axi_adrv9001/adrv9001_aligner4.v +++ b/library/axi_adrv9001/adrv9001_aligner4.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_aligner8.v b/library/axi_adrv9001/adrv9001_aligner8.v index 26b21926f..e4f41524f 100644 --- a/library/axi_adrv9001/adrv9001_aligner8.v +++ b/library/axi_adrv9001/adrv9001_aligner8.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_pack.v b/library/axi_adrv9001/adrv9001_pack.v index 981ccdd96..659c5e8e3 100644 --- a/library/axi_adrv9001/adrv9001_pack.v +++ b/library/axi_adrv9001/adrv9001_pack.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_rx.v b/library/axi_adrv9001/adrv9001_rx.v index 8de38a1a4..7f9dc3f1c 100644 --- a/library/axi_adrv9001/adrv9001_rx.v +++ b/library/axi_adrv9001/adrv9001_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_rx_link.v b/library/axi_adrv9001/adrv9001_rx_link.v index 34c76a80a..467d5631f 100644 --- a/library/axi_adrv9001/adrv9001_rx_link.v +++ b/library/axi_adrv9001/adrv9001_rx_link.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_tx.v b/library/axi_adrv9001/adrv9001_tx.v index 830586283..602fc1ea1 100644 --- a/library/axi_adrv9001/adrv9001_tx.v +++ b/library/axi_adrv9001/adrv9001_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_tx_link.v b/library/axi_adrv9001/adrv9001_tx_link.v index cd9b0d358..d8882c121 100644 --- a/library/axi_adrv9001/adrv9001_tx_link.v +++ b/library/axi_adrv9001/adrv9001_tx_link.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v index d77145f4a..cdacf6c62 100644 --- a/library/axi_adrv9001/axi_adrv9001.v +++ b/library/axi_adrv9001/axi_adrv9001.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index 5fc21cb9a..7168f7bcf 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001_if.v b/library/axi_adrv9001/axi_adrv9001_if.v index 2cde66176..bfe467773 100644 --- a/library/axi_adrv9001/axi_adrv9001_if.v +++ b/library/axi_adrv9001/axi_adrv9001_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001_rx.v b/library/axi_adrv9001/axi_adrv9001_rx.v index bdacc2f70..68b4dc904 100644 --- a/library/axi_adrv9001/axi_adrv9001_rx.v +++ b/library/axi_adrv9001/axi_adrv9001_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001_rx_channel.v b/library/axi_adrv9001/axi_adrv9001_rx_channel.v index 4844960ca..e8abe2013 100644 --- a/library/axi_adrv9001/axi_adrv9001_rx_channel.v +++ b/library/axi_adrv9001/axi_adrv9001_rx_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001_tdd.v b/library/axi_adrv9001/axi_adrv9001_tdd.v index 0e700cd93..556850982 100644 --- a/library/axi_adrv9001/axi_adrv9001_tdd.v +++ b/library/axi_adrv9001/axi_adrv9001_tdd.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v index 748edd721..3e37b455b 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx.v +++ b/library/axi_adrv9001/axi_adrv9001_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001_tx_channel.v b/library/axi_adrv9001/axi_adrv9001_tx_channel.v index c5d838ace..b23a148e7 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx_channel.v +++ b/library/axi_adrv9001/axi_adrv9001_tx_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/intel/adrv9001_rx.v b/library/axi_adrv9001/intel/adrv9001_rx.v index 6cc7bd687..8b01f1e49 100644 --- a/library/axi_adrv9001/intel/adrv9001_rx.v +++ b/library/axi_adrv9001/intel/adrv9001_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/intel/adrv9001_tx.v b/library/axi_adrv9001/intel/adrv9001_tx.v index 0e559b380..0f4663528 100644 --- a/library/axi_adrv9001/intel/adrv9001_tx.v +++ b/library/axi_adrv9001/intel/adrv9001_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v index f407e98d5..80dc440f3 100644 --- a/library/axi_clkgen/axi_clkgen.v +++ b/library/axi_clkgen/axi_clkgen.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_clock_monitor/axi_clock_monitor.v b/library/axi_clock_monitor/axi_clock_monitor.v index 94e7bff67..2128cc06c 100755 --- a/library/axi_clock_monitor/axi_clock_monitor.v +++ b/library/axi_clock_monitor/axi_clock_monitor.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/axi_dac_interpolate/axi_dac_interpolate.v b/library/axi_dac_interpolate/axi_dac_interpolate.v index 92d8f807e..2077b1017 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_filter.v b/library/axi_dac_interpolate/axi_dac_interpolate_filter.v index 01914878d..0f746959b 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate_filter.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate_filter.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v index 015fd3f1b..01fecec1e 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v index 8d22e4f00..8a8d7035a 100644 --- a/library/axi_dmac/address_generator.v +++ b/library/axi_dmac/address_generator.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index e27d1dabf..88218e37e 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac_burst_memory.v b/library/axi_dmac/axi_dmac_burst_memory.v index 60ace8453..5e0123b16 100644 --- a/library/axi_dmac/axi_dmac_burst_memory.v +++ b/library/axi_dmac/axi_dmac_burst_memory.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac_regmap.v b/library/axi_dmac/axi_dmac_regmap.v index 05bc46789..e26380dac 100644 --- a/library/axi_dmac/axi_dmac_regmap.v +++ b/library/axi_dmac/axi_dmac_regmap.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac_regmap_request.v b/library/axi_dmac/axi_dmac_regmap_request.v index 63f809683..adb240a2f 100644 --- a/library/axi_dmac/axi_dmac_regmap_request.v +++ b/library/axi_dmac/axi_dmac_regmap_request.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac_reset_manager.v b/library/axi_dmac/axi_dmac_reset_manager.v index 8f6193066..ac3ca6872 100644 --- a/library/axi_dmac/axi_dmac_reset_manager.v +++ b/library/axi_dmac/axi_dmac_reset_manager.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac_resize_dest.v b/library/axi_dmac/axi_dmac_resize_dest.v index b185386ed..d734c11be 100644 --- a/library/axi_dmac/axi_dmac_resize_dest.v +++ b/library/axi_dmac/axi_dmac_resize_dest.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac_resize_src.v b/library/axi_dmac/axi_dmac_resize_src.v index 09ea81be9..761446f9e 100644 --- a/library/axi_dmac/axi_dmac_resize_src.v +++ b/library/axi_dmac/axi_dmac_resize_src.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac_response_manager.v b/library/axi_dmac/axi_dmac_response_manager.v index e1f478a5f..333d9212b 100644 --- a/library/axi_dmac/axi_dmac_response_manager.v +++ b/library/axi_dmac/axi_dmac_response_manager.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/axi_dmac_transfer.v b/library/axi_dmac/axi_dmac_transfer.v index 4f82ea29e..352858c1a 100644 --- a/library/axi_dmac/axi_dmac_transfer.v +++ b/library/axi_dmac/axi_dmac_transfer.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/axi_dmac/axi_register_slice.v b/library/axi_dmac/axi_register_slice.v index d3de9a1c8..e5712224f 100644 --- a/library/axi_dmac/axi_register_slice.v +++ b/library/axi_dmac/axi_register_slice.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index a23f16e9a..109800084 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/dest_axi_mm.v b/library/axi_dmac/dest_axi_mm.v index f162d48ad..b826a350a 100644 --- a/library/axi_dmac/dest_axi_mm.v +++ b/library/axi_dmac/dest_axi_mm.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v index 508e9ad1c..2f38f9e1a 100644 --- a/library/axi_dmac/dest_axi_stream.v +++ b/library/axi_dmac/dest_axi_stream.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v index fe2a74758..65b9fdca3 100644 --- a/library/axi_dmac/dest_fifo_inf.v +++ b/library/axi_dmac/dest_fifo_inf.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/dmac_2d_transfer.v b/library/axi_dmac/dmac_2d_transfer.v index d3bf81638..cf87ca39d 100644 --- a/library/axi_dmac/dmac_2d_transfer.v +++ b/library/axi_dmac/dmac_2d_transfer.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 06a4091bc..9b6ad6c0f 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v index 0296fca88..2951e244e 100644 --- a/library/axi_dmac/request_generator.v +++ b/library/axi_dmac/request_generator.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/response_generator.v b/library/axi_dmac/response_generator.v index d17f6a7a3..856233616 100644 --- a/library/axi_dmac/response_generator.v +++ b/library/axi_dmac/response_generator.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/response_handler.v b/library/axi_dmac/response_handler.v index a45f29edf..dae856979 100644 --- a/library/axi_dmac/response_handler.v +++ b/library/axi_dmac/response_handler.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/splitter.v b/library/axi_dmac/splitter.v index 7f10dcc72..93e2cfe31 100644 --- a/library/axi_dmac/splitter.v +++ b/library/axi_dmac/splitter.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v index abdb275b8..e3cd4e028 100644 --- a/library/axi_dmac/src_axi_mm.v +++ b/library/axi_dmac/src_axi_mm.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/src_axi_stream.v b/library/axi_dmac/src_axi_stream.v index fe64609e9..d83c151c7 100644 --- a/library/axi_dmac/src_axi_stream.v +++ b/library/axi_dmac/src_axi_stream.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v index 6a04bbd04..b5af3bfae 100644 --- a/library/axi_dmac/src_fifo_inf.v +++ b/library/axi_dmac/src_fifo_inf.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/axi_read_slave.v b/library/axi_dmac/tb/axi_read_slave.v index 8c8d6d39f..2aa47b0e2 100644 --- a/library/axi_dmac/tb/axi_read_slave.v +++ b/library/axi_dmac/tb/axi_read_slave.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/axi_slave.v b/library/axi_dmac/tb/axi_slave.v index aa2191a47..fc5199a11 100644 --- a/library/axi_dmac/tb/axi_slave.v +++ b/library/axi_dmac/tb/axi_slave.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/axi_write_slave.v b/library/axi_dmac/tb/axi_write_slave.v index 646bafdbd..06523220a 100644 --- a/library/axi_dmac/tb/axi_write_slave.v +++ b/library/axi_dmac/tb/axi_write_slave.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/dma_read_shutdown_tb.v b/library/axi_dmac/tb/dma_read_shutdown_tb.v index 4dce05dc2..c7568c5dd 100644 --- a/library/axi_dmac/tb/dma_read_shutdown_tb.v +++ b/library/axi_dmac/tb/dma_read_shutdown_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/dma_read_tb.v b/library/axi_dmac/tb/dma_read_tb.v index 0cbc81562..29e8ae427 100644 --- a/library/axi_dmac/tb/dma_read_tb.v +++ b/library/axi_dmac/tb/dma_read_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/dma_write_shutdown_tb.v b/library/axi_dmac/tb/dma_write_shutdown_tb.v index 76dff6e89..eaefcb2a0 100644 --- a/library/axi_dmac/tb/dma_write_shutdown_tb.v +++ b/library/axi_dmac/tb/dma_write_shutdown_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/dma_write_tb.v b/library/axi_dmac/tb/dma_write_tb.v index b228b5e22..213191355 100644 --- a/library/axi_dmac/tb/dma_write_tb.v +++ b/library/axi_dmac/tb/dma_write_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/regmap_tb.v b/library/axi_dmac/tb/regmap_tb.v index 9dc4e38a3..ae34be530 100644 --- a/library/axi_dmac/tb/regmap_tb.v +++ b/library/axi_dmac/tb/regmap_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/reset_manager_tb.v b/library/axi_dmac/tb/reset_manager_tb.v index 85b426c44..b14c1c7ac 100644 --- a/library/axi_dmac/tb/reset_manager_tb.v +++ b/library/axi_dmac/tb/reset_manager_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_dmac/tb/tb_base.v b/library/axi_dmac/tb/tb_base.v index e6dd7ad93..f12267d24 100644 --- a/library/axi_dmac/tb/tb_base.v +++ b/library/axi_dmac/tb/tb_base.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_fan_control/axi_fan_control.v b/library/axi_fan_control/axi_fan_control.v index 72a955443..cd03f6c0f 100644 --- a/library/axi_fan_control/axi_fan_control.v +++ b/library/axi_fan_control/axi_fan_control.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v index d6f227227..e88ed4962 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v index 7c71be7ac..f56465311 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v index 3e7228e7b..551d3e8b0 100644 --- a/library/axi_generic_adc/axi_generic_adc.v +++ b/library/axi_generic_adc/axi_generic_adc.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_gpreg/axi_gpreg.v b/library/axi_gpreg/axi_gpreg.v index 83c797aa1..7650e01f7 100644 --- a/library/axi_gpreg/axi_gpreg.v +++ b/library/axi_gpreg/axi_gpreg.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_gpreg/axi_gpreg_clock_mon.v b/library/axi_gpreg/axi_gpreg_clock_mon.v index bc3380bce..022aab7e1 100644 --- a/library/axi_gpreg/axi_gpreg_clock_mon.v +++ b/library/axi_gpreg/axi_gpreg_clock_mon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_gpreg/axi_gpreg_io.v b/library/axi_gpreg/axi_gpreg_io.v index 445fdc29c..1483e68a7 100644 --- a/library/axi_gpreg/axi_gpreg_io.v +++ b/library/axi_gpreg/axi_gpreg_io.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_hdmi_rx/axi_hdmi_rx.v b/library/axi_hdmi_rx/axi_hdmi_rx.v index 70f3de414..3640be4ad 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_core.v b/library/axi_hdmi_rx/axi_hdmi_rx_core.v index abe93ad7c..a74e5c592 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_core.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_core.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_es.v b/library/axi_hdmi_rx/axi_hdmi_rx_es.v index 416f91019..8de1ad256 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_es.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_es.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v b/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v index c5a859eec..7774c8850 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index c5df537ba..55b602655 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v index 38f1ed298..ccbe3c8d3 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_es.v b/library/axi_hdmi_tx/axi_hdmi_tx_es.v index 46a6bf5a7..69e85f4d0 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_es.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_es.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v b/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v index d8f7ae95f..2308ec2c1 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_intr_monitor/axi_intr_monitor.v b/library/axi_intr_monitor/axi_intr_monitor.v index c3785158d..0b01628f4 100644 --- a/library/axi_intr_monitor/axi_intr_monitor.v +++ b/library/axi_intr_monitor/axi_intr_monitor.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_laser_driver/axi_laser_driver.v b/library/axi_laser_driver/axi_laser_driver.v index abb2c11b0..1bf551982 100644 --- a/library/axi_laser_driver/axi_laser_driver.v +++ b/library/axi_laser_driver/axi_laser_driver.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_laser_driver/axi_laser_driver_regmap.v b/library/axi_laser_driver/axi_laser_driver_regmap.v index c756a83ba..fb84faece 100644 --- a/library/axi_laser_driver/axi_laser_driver_regmap.v +++ b/library/axi_laser_driver/axi_laser_driver_regmap.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v index 709b0bcf5..64be96456 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_reg.v b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v index 582db1d0d..5b860b8fe 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer_reg.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v index cb28b875c..38293dfa6 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ltc2387/axi_ltc2387.v b/library/axi_ltc2387/axi_ltc2387.v index 66872d8be..11aec1987 100644 --- a/library/axi_ltc2387/axi_ltc2387.v +++ b/library/axi_ltc2387/axi_ltc2387.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ltc2387/axi_ltc2387_channel.v b/library/axi_ltc2387/axi_ltc2387_channel.v index 5a4e9c86c..8bad30f67 100644 --- a/library/axi_ltc2387/axi_ltc2387_channel.v +++ b/library/axi_ltc2387/axi_ltc2387_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ltc2387/axi_ltc2387_if.v b/library/axi_ltc2387/axi_ltc2387_if.v index c9afb3d33..0efd5e1f3 100644 --- a/library/axi_ltc2387/axi_ltc2387_if.v +++ b/library/axi_ltc2387/axi_ltc2387_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_pulse_gen/axi_pulse_gen.v b/library/axi_pulse_gen/axi_pulse_gen.v index 80ddd5398..3aebe0a82 100644 --- a/library/axi_pulse_gen/axi_pulse_gen.v +++ b/library/axi_pulse_gen/axi_pulse_gen.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_pulse_gen/axi_pulse_gen_regmap.v b/library/axi_pulse_gen/axi_pulse_gen_regmap.v index 678863eb7..e276276fb 100644 --- a/library/axi_pulse_gen/axi_pulse_gen_regmap.v +++ b/library/axi_pulse_gen/axi_pulse_gen_regmap.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_pwm_gen/axi_pwm_gen.v b/library/axi_pwm_gen/axi_pwm_gen.v index 1175aa33c..14fc60b14 100644 --- a/library/axi_pwm_gen/axi_pwm_gen.v +++ b/library/axi_pwm_gen/axi_pwm_gen.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_pwm_gen/axi_pwm_gen_1.v b/library/axi_pwm_gen/axi_pwm_gen_1.v index 668139d0b..0ba775de7 100644 --- a/library/axi_pwm_gen/axi_pwm_gen_1.v +++ b/library/axi_pwm_gen/axi_pwm_gen_1.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_pwm_gen/axi_pwm_gen_regmap.v b/library/axi_pwm_gen/axi_pwm_gen_regmap.v index 75f132673..0d81d0664 100644 --- a/library/axi_pwm_gen/axi_pwm_gen_regmap.v +++ b/library/axi_pwm_gen/axi_pwm_gen_regmap.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v b/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v index a5c69019e..e541891af 100644 --- a/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v +++ b/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_sysid/axi_sysid.v b/library/axi_sysid/axi_sysid.v index b80eada8c..dbb522837 100755 --- a/library/axi_sysid/axi_sysid.v +++ b/library/axi_sysid/axi_sysid.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2019 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_tdd/axi_tdd.sv b/library/axi_tdd/axi_tdd.sv index 81591b7df..532f1e3fa 100644 --- a/library/axi_tdd/axi_tdd.sv +++ b/library/axi_tdd/axi_tdd.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_tdd/axi_tdd_channel.sv b/library/axi_tdd/axi_tdd_channel.sv index e33f9bb84..668dd6724 100644 --- a/library/axi_tdd/axi_tdd_channel.sv +++ b/library/axi_tdd/axi_tdd_channel.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_tdd/axi_tdd_counter.sv b/library/axi_tdd/axi_tdd_counter.sv index d3a02983a..0ba133e82 100644 --- a/library/axi_tdd/axi_tdd_counter.sv +++ b/library/axi_tdd/axi_tdd_counter.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_tdd/axi_tdd_pkg.sv b/library/axi_tdd/axi_tdd_pkg.sv index 1ff49925b..5546f74af 100644 --- a/library/axi_tdd/axi_tdd_pkg.sv +++ b/library/axi_tdd/axi_tdd_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_tdd/axi_tdd_regmap.sv b/library/axi_tdd/axi_tdd_regmap.sv index 4a2a0a94f..4dd36c951 100644 --- a/library/axi_tdd/axi_tdd_regmap.sv +++ b/library/axi_tdd/axi_tdd_regmap.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_tdd/axi_tdd_sync_gen.sv b/library/axi_tdd/axi_tdd_sync_gen.sv index 44276ebbd..02f955a8e 100644 --- a/library/axi_tdd/axi_tdd_sync_gen.sv +++ b/library/axi_tdd/axi_tdd_sync_gen.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v index 07d73f6a8..d96dc3e24 100644 --- a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v +++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v index 086ef87b9..ab597253e 100644 --- a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v +++ b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_3w_spi.v b/library/common/ad_3w_spi.v index e5c72e10b..bd7cb4b48 100644 --- a/library/common/ad_3w_spi.v +++ b/library/common/ad_3w_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_addsub.v b/library/common/ad_addsub.v index e149e088c..8b515973f 100644 --- a/library/common/ad_addsub.v +++ b/library/common/ad_addsub.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_adl5904_rst.v b/library/common/ad_adl5904_rst.v index c0300293b..1b305f85c 100644 --- a/library/common/ad_adl5904_rst.v +++ b/library/common/ad_adl5904_rst.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_axis_inf_rx.v b/library/common/ad_axis_inf_rx.v index 5f6d2c514..8da4105ac 100644 --- a/library/common/ad_axis_inf_rx.v +++ b/library/common/ad_axis_inf_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_b2g.v b/library/common/ad_b2g.v index db0aaa604..5fcadfe42 100644 --- a/library/common/ad_b2g.v +++ b/library/common/ad_b2g.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_bus_mux.v b/library/common/ad_bus_mux.v index 656da1c3e..95336bb7f 100644 --- a/library/common/ad_bus_mux.v +++ b/library/common/ad_bus_mux.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_csc.v b/library/common/ad_csc.v index 05a923815..a9aac8b3f 100644 --- a/library/common/ad_csc.v +++ b/library/common/ad_csc.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_csc_CrYCb2RGB.v b/library/common/ad_csc_CrYCb2RGB.v index 8400edd0f..184966e92 100644 --- a/library/common/ad_csc_CrYCb2RGB.v +++ b/library/common/ad_csc_CrYCb2RGB.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_csc_RGB2CrYCb.v b/library/common/ad_csc_RGB2CrYCb.v index 40bc77ffe..387bef45a 100644 --- a/library/common/ad_csc_RGB2CrYCb.v +++ b/library/common/ad_csc_RGB2CrYCb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_datafmt.v b/library/common/ad_datafmt.v index 37f5d265e..0859e2658 100644 --- a/library/common/ad_datafmt.v +++ b/library/common/ad_datafmt.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v index 39ed6d8ed..59670df41 100644 --- a/library/common/ad_dds.v +++ b/library/common/ad_dds.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_dds_1.v b/library/common/ad_dds_1.v index e511bb779..59b299f4a 100644 --- a/library/common/ad_dds_1.v +++ b/library/common/ad_dds_1.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_dds_2.v b/library/common/ad_dds_2.v index 04ba1e981..db7801d6a 100644 --- a/library/common/ad_dds_2.v +++ b/library/common/ad_dds_2.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_dds_cordic_pipe.v b/library/common/ad_dds_cordic_pipe.v index 47d0e4ef2..2bff8a22e 100644 --- a/library/common/ad_dds_cordic_pipe.v +++ b/library/common/ad_dds_cordic_pipe.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_dds_sine.v b/library/common/ad_dds_sine.v index 40dbb84ab..68696305a 100644 --- a/library/common/ad_dds_sine.v +++ b/library/common/ad_dds_sine.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_dds_sine_cordic.v b/library/common/ad_dds_sine_cordic.v index 2ba6ce0bf..33f1e10fe 100644 --- a/library/common/ad_dds_sine_cordic.v +++ b/library/common/ad_dds_sine_cordic.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_edge_detect.v b/library/common/ad_edge_detect.v index 1cffa0449..f1cac88bf 100644 --- a/library/common/ad_edge_detect.v +++ b/library/common/ad_edge_detect.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_g2b.v b/library/common/ad_g2b.v index d0f3e57b5..373b87284 100644 --- a/library/common/ad_g2b.v +++ b/library/common/ad_g2b.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_iobuf.v b/library/common/ad_iobuf.v index a93628201..c097a3fee 100644 --- a/library/common/ad_iobuf.v +++ b/library/common/ad_iobuf.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_iqcor.v b/library/common/ad_iqcor.v index b8737f40b..02d2ca453 100644 --- a/library/common/ad_iqcor.v +++ b/library/common/ad_iqcor.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_mem.v b/library/common/ad_mem.v index f3825d2b4..2cf05d589 100644 --- a/library/common/ad_mem.v +++ b/library/common/ad_mem.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_mem_asym.v b/library/common/ad_mem_asym.v index 196365037..f18091ff4 100644 --- a/library/common/ad_mem_asym.v +++ b/library/common/ad_mem_asym.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_mux.v b/library/common/ad_mux.v index e0842e38d..ffcdd7ad8 100644 --- a/library/common/ad_mux.v +++ b/library/common/ad_mux.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_mux_core.v b/library/common/ad_mux_core.v index 7663b247c..d718aa724 100644 --- a/library/common/ad_mux_core.v +++ b/library/common/ad_mux_core.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_pack.v b/library/common/ad_pack.v index 4342427b3..8a7ddbb12 100644 --- a/library/common/ad_pack.v +++ b/library/common/ad_pack.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_perfect_shuffle.v b/library/common/ad_perfect_shuffle.v index c04276515..37987e697 100644 --- a/library/common/ad_perfect_shuffle.v +++ b/library/common/ad_perfect_shuffle.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // Each core or library found in this collection may have its own licensing terms. // The user should keep this in in mind while exploring these cores. diff --git a/library/common/ad_pngen.v b/library/common/ad_pngen.v index c3c59263a..f7280b3d9 100644 --- a/library/common/ad_pngen.v +++ b/library/common/ad_pngen.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/common/ad_pnmon.v b/library/common/ad_pnmon.v index f44f2c81e..7a223c504 100644 --- a/library/common/ad_pnmon.v +++ b/library/common/ad_pnmon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_pps_receiver.v b/library/common/ad_pps_receiver.v index 9927cf1f2..095bc31a3 100644 --- a/library/common/ad_pps_receiver.v +++ b/library/common/ad_pps_receiver.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_rst.v b/library/common/ad_rst.v index f0d75aaac..1aa108900 100644 --- a/library/common/ad_rst.v +++ b/library/common/ad_rst.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_ss_422to444.v b/library/common/ad_ss_422to444.v index 78c369689..ec2f66b66 100644 --- a/library/common/ad_ss_422to444.v +++ b/library/common/ad_ss_422to444.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_ss_444to422.v b/library/common/ad_ss_444to422.v index 9e91cae70..7aa6b3c77 100644 --- a/library/common/ad_ss_444to422.v +++ b/library/common/ad_ss_444to422.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_sysref_gen.v b/library/common/ad_sysref_gen.v index aa951d2ec..1367f5a92 100644 --- a/library/common/ad_sysref_gen.v +++ b/library/common/ad_sysref_gen.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v index edd5046fc..46d231750 100644 --- a/library/common/ad_tdd_control.v +++ b/library/common/ad_tdd_control.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_upack.v b/library/common/ad_upack.v index b8218863f..ecb62eebd 100644 --- a/library/common/ad_upack.v +++ b/library/common/ad_upack.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/ad_xcvr_rx_if.v b/library/common/ad_xcvr_rx_if.v index 0764a1760..8bbd3f86e 100644 --- a/library/common/ad_xcvr_rx_if.v +++ b/library/common/ad_xcvr_rx_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/tb/ad_mux_tb.v b/library/common/tb/ad_mux_tb.v index 126c11d36..08e131588 100644 --- a/library/common/tb/ad_mux_tb.v +++ b/library/common/tb/ad_mux_tb.v @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `timescale 1ns/100ps module ad_mux_tb; diff --git a/library/common/tb/ad_pack_tb.v b/library/common/tb/ad_pack_tb.v index 6cf271961..0105cd6ba 100644 --- a/library/common/tb/ad_pack_tb.v +++ b/library/common/tb/ad_pack_tb.v @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `timescale 1ns/100ps module ad_pack_tb; diff --git a/library/common/tb/ad_upack_tb.v b/library/common/tb/ad_upack_tb.v index 0acf61e65..2289af2ec 100644 --- a/library/common/tb/ad_upack_tb.v +++ b/library/common/tb/ad_upack_tb.v @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `timescale 1ns/100ps module ad_upack_tb; diff --git a/library/common/up_adc_channel.v b/library/common/up_adc_channel.v index fd66bf33e..f38c60453 100644 --- a/library/common/up_adc_channel.v +++ b/library/common/up_adc_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index 87ddf067d..7479f2b70 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_axi.v b/library/common/up_axi.v index 118fb80c2..6b071f427 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_clkgen.v b/library/common/up_clkgen.v index 30548dc20..f3f3bfbb5 100644 --- a/library/common/up_clkgen.v +++ b/library/common/up_clkgen.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_clock_mon.v b/library/common/up_clock_mon.v index 272c4e719..5c4c21078 100644 --- a/library/common/up_clock_mon.v +++ b/library/common/up_clock_mon.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v index 269e8a080..eddd19eb5 100644 --- a/library/common/up_dac_channel.v +++ b/library/common/up_dac_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v index de18ea57f..1e4f29c81 100644 --- a/library/common/up_dac_common.v +++ b/library/common/up_dac_common.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_delay_cntrl.v b/library/common/up_delay_cntrl.v index 9c3af4466..f50be757a 100644 --- a/library/common/up_delay_cntrl.v +++ b/library/common/up_delay_cntrl.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_hdmi_rx.v b/library/common/up_hdmi_rx.v index fc714e49b..480179569 100644 --- a/library/common/up_hdmi_rx.v +++ b/library/common/up_hdmi_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v index 09d1b28d1..009330dad 100644 --- a/library/common/up_hdmi_tx.v +++ b/library/common/up_hdmi_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_pmod.v b/library/common/up_pmod.v index 7a8e6565c..278200e08 100644 --- a/library/common/up_pmod.v +++ b/library/common/up_pmod.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index d44e6b89a..bd05c3861 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_xfer_cntrl.v b/library/common/up_xfer_cntrl.v index f38e9b048..3700157cc 100644 --- a/library/common/up_xfer_cntrl.v +++ b/library/common/up_xfer_cntrl.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/up_xfer_status.v b/library/common/up_xfer_status.v index 3b0bafe3d..715082a12 100644 --- a/library/common/up_xfer_status.v +++ b/library/common/up_xfer_status.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/util_axis_upscale.v b/library/common/util_axis_upscale.v index 1822b4120..499d1f865 100644 --- a/library/common/util_axis_upscale.v +++ b/library/common/util_axis_upscale.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/util_dec256sinc24b.v b/library/common/util_dec256sinc24b.v index c7f63b894..5754da246 100644 --- a/library/common/util_dec256sinc24b.v +++ b/library/common/util_dec256sinc24b.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/common/util_delay.v b/library/common/util_delay.v index b19395948..874049b66 100644 --- a/library/common/util_delay.v +++ b/library/common/util_delay.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/common/util_ext_sync.v b/library/common/util_ext_sync.v index 6a3002fb9..8c299bac4 100644 --- a/library/common/util_ext_sync.v +++ b/library/common/util_ext_sync.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/common/util_pulse_gen.v b/library/common/util_pulse_gen.v index 0dd1d752f..d323cec6e 100644 --- a/library/common/util_pulse_gen.v +++ b/library/common/util_pulse_gen.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/cordic_demod/cordic_demod.v b/library/cordic_demod/cordic_demod.v index 029c5a692..809cabc8f 100644 --- a/library/cordic_demod/cordic_demod.v +++ b/library/cordic_demod/cordic_demod.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/data_offload/data_offload.v b/library/data_offload/data_offload.v index 490c32ce5..6f084b8ad 100644 --- a/library/data_offload/data_offload.v +++ b/library/data_offload/data_offload.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/data_offload/data_offload_fsm.v b/library/data_offload/data_offload_fsm.v index 242ee374b..3bccddc99 100644 --- a/library/data_offload/data_offload_fsm.v +++ b/library/data_offload/data_offload_fsm.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/data_offload/data_offload_regmap.v b/library/data_offload/data_offload_regmap.v index 23d740053..dc3ea1772 100644 --- a/library/data_offload/data_offload_regmap.v +++ b/library/data_offload/data_offload_regmap.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/adi_jesd204/adi_jesd204_glue.v b/library/intel/adi_jesd204/adi_jesd204_glue.v index a293c7959..9ebf40ef4 100644 --- a/library/intel/adi_jesd204/adi_jesd204_glue.v +++ b/library/intel/adi_jesd204/adi_jesd204_glue.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/avl_adxcfg/avl_adxcfg.v b/library/intel/avl_adxcfg/avl_adxcfg.v index 47f4df107..af903946f 100644 --- a/library/intel/avl_adxcfg/avl_adxcfg.v +++ b/library/intel/avl_adxcfg/avl_adxcfg.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v b/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v index 6008de3bf..0b6030f4d 100644 --- a/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v +++ b/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/avl_adxphy/avl_adxphy.v b/library/intel/avl_adxphy/avl_adxphy.v index bb74ee78c..dc371c985 100644 --- a/library/intel/avl_adxphy/avl_adxphy.v +++ b/library/intel/avl_adxphy/avl_adxphy.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/avl_dacfifo/avl_dacfifo.v b/library/intel/avl_dacfifo/avl_dacfifo.v index 7d2bb2216..258ae14fd 100644 --- a/library/intel/avl_dacfifo/avl_dacfifo.v +++ b/library/intel/avl_dacfifo/avl_dacfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/avl_dacfifo/avl_dacfifo_rd.v b/library/intel/avl_dacfifo/avl_dacfifo_rd.v index 93d7e8ce7..722b98b34 100644 --- a/library/intel/avl_dacfifo/avl_dacfifo_rd.v +++ b/library/intel/avl_dacfifo/avl_dacfifo_rd.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/avl_dacfifo/avl_dacfifo_wr.v b/library/intel/avl_dacfifo/avl_dacfifo_wr.v index 079e7b385..21ec8c841 100644 --- a/library/intel/avl_dacfifo/avl_dacfifo_wr.v +++ b/library/intel/avl_dacfifo/avl_dacfifo_wr.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/avl_dacfifo/util_dacfifo_bypass.v b/library/intel/avl_dacfifo/util_dacfifo_bypass.v index fcde2b10b..9e01510de 100644 --- a/library/intel/avl_dacfifo/util_dacfifo_bypass.v +++ b/library/intel/avl_dacfifo/util_dacfifo_bypass.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/axi_adxcvr/axi_adxcvr.v b/library/intel/axi_adxcvr/axi_adxcvr.v index fb794926c..cb54ffa3c 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr.v +++ b/library/intel/axi_adxcvr/axi_adxcvr.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/axi_adxcvr/axi_adxcvr_up.v b/library/intel/axi_adxcvr/axi_adxcvr_up.v index 4afec634b..366e71366 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr_up.v +++ b/library/intel/axi_adxcvr/axi_adxcvr_up.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/common/ad_dcfilter.v b/library/intel/common/ad_dcfilter.v index 188f08529..c135f35b3 100644 --- a/library/intel/common/ad_dcfilter.v +++ b/library/intel/common/ad_dcfilter.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/common/ad_mul.v b/library/intel/common/ad_mul.v index 3757b52b4..7359ec90d 100644 --- a/library/intel/common/ad_mul.v +++ b/library/intel/common/ad_mul.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/jesd204_phy/jesd204_phy_glue.v b/library/intel/jesd204_phy/jesd204_phy_glue.v index 6dce1717c..28e2244b5 100644 --- a/library/intel/jesd204_phy/jesd204_phy_glue.v +++ b/library/intel/jesd204_phy/jesd204_phy_glue.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/intel/util_clkdiv/util_clkdiv.v b/library/intel/util_clkdiv/util_clkdiv.v index acd334c63..2c6836a98 100644 --- a/library/intel/util_clkdiv/util_clkdiv.v +++ b/library/intel/util_clkdiv/util_clkdiv.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v index f32aee836..bd2bac0c7 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v index 84d77800a..4a4b8a8a8 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v index bd16982e1..c5e6aa2b2 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v index 197a10976..c477aa171 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v index a1c14d93c..88ae6b36c 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v index f3f59c3f1..1b878c8ec 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018-2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v b/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v index 545155b00..f0d8de0d9 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v +++ b/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v index 5ebf90207..b8751eca5 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v index adb952613..b2d90ef54 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v index 24ed27b8b..3563e1806 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v index 9a84574cd..242c1f4e8 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v index 1ea887c5f..70c540f6c 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v index 16d24329e..77679c199 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 7a1a23af5..77e3d9b4a 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v b/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v index 3731ac6fe..04a3356d4 100644 --- a/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v +++ b/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v index 04e26b827..cb9ded906 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v index 304b8e8c4..85d1d1d44 100644 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v index 544649d83..a15dfc18e 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/sysid_rom/sysid_rom.v b/library/sysid_rom/sysid_rom.v index 62c5ced2e..fd15e9936 100755 --- a/library/sysid_rom/sysid_rom.v +++ b/library/sysid_rom/sysid_rom.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2019 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_adcfifo/util_adcfifo.v b/library/util_adcfifo/util_adcfifo.v index 5239e8aa3..f0396d4bd 100644 --- a/library/util_adcfifo/util_adcfifo.v +++ b/library/util_adcfifo/util_adcfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v index 79f2ca553..20cccf992 100644 --- a/library/util_axis_fifo/util_axis_fifo.v +++ b/library/util_axis_fifo/util_axis_fifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_axis_fifo/util_axis_fifo_address_generator.v b/library/util_axis_fifo/util_axis_fifo_address_generator.v index 10c56d747..4e3546173 100644 --- a/library/util_axis_fifo/util_axis_fifo_address_generator.v +++ b/library/util_axis_fifo/util_axis_fifo_address_generator.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_axis_fifo_asym/util_axis_fifo_asym.v b/library/util_axis_fifo_asym/util_axis_fifo_asym.v index 9fdfedd18..888f87deb 100644 --- a/library/util_axis_fifo_asym/util_axis_fifo_asym.v +++ b/library/util_axis_fifo_asym/util_axis_fifo_asym.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_axis_resize/util_axis_resize.v b/library/util_axis_resize/util_axis_resize.v index d23b201d9..0a5b1042b 100644 --- a/library/util_axis_resize/util_axis_resize.v +++ b/library/util_axis_resize/util_axis_resize.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_bsplit/util_bsplit.v b/library/util_bsplit/util_bsplit.v index 1ae0d8fb4..4371e2c1c 100644 --- a/library/util_bsplit/util_bsplit.v +++ b/library/util_bsplit/util_bsplit.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_cdc/sync_bits.v b/library/util_cdc/sync_bits.v index 3d2a4566f..d6bd616c9 100644 --- a/library/util_cdc/sync_bits.v +++ b/library/util_cdc/sync_bits.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_cdc/sync_data.v b/library/util_cdc/sync_data.v index 5f13ac032..a9f7c1db5 100644 --- a/library/util_cdc/sync_data.v +++ b/library/util_cdc/sync_data.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_cdc/sync_event.v b/library/util_cdc/sync_event.v index d0d051205..8c93fe5a7 100644 --- a/library/util_cdc/sync_event.v +++ b/library/util_cdc/sync_event.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_cdc/sync_gray.v b/library/util_cdc/sync_gray.v index f16cfff4a..a60e85594 100644 --- a/library/util_cdc/sync_gray.v +++ b/library/util_cdc/sync_gray.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_cic/cic_comb.v b/library/util_cic/cic_comb.v index 5a3b32777..de176ceb0 100644 --- a/library/util_cic/cic_comb.v +++ b/library/util_cic/cic_comb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_cic/cic_int.v b/library/util_cic/cic_int.v index da2e7bb30..06fbd8fd8 100644 --- a/library/util_cic/cic_int.v +++ b/library/util_cic/cic_int.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index c9555e67f..e17f94692 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_dacfifo/util_dacfifo_bypass.v b/library/util_dacfifo/util_dacfifo_bypass.v index bcc9f2e8c..eb5e2459c 100644 --- a/library/util_dacfifo/util_dacfifo_bypass.v +++ b/library/util_dacfifo/util_dacfifo_bypass.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_do_ram/util_do_ram.v b/library/util_do_ram/util_do_ram.v index c5ec831e6..6e91233bd 100644 --- a/library/util_do_ram/util_do_ram.v +++ b/library/util_do_ram/util_do_ram.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_extract/util_extract.v b/library/util_extract/util_extract.v index a4f55dd93..1058e62b5 100644 --- a/library/util_extract/util_extract.v +++ b/library/util_extract/util_extract.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_fir_dec/util_fir_dec.v b/library/util_fir_dec/util_fir_dec.v index 66771c433..04a68ce26 100644 --- a/library/util_fir_dec/util_fir_dec.v +++ b/library/util_fir_dec/util_fir_dec.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v index 362f8b9ca..9ad4ab203 100644 --- a/library/util_fir_int/util_fir_int.v +++ b/library/util_fir_int/util_fir_int.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_gmii_to_rgmii/mdc_mdio.v b/library/util_gmii_to_rgmii/mdc_mdio.v index db698a9e1..32099d967 100644 --- a/library/util_gmii_to_rgmii/mdc_mdio.v +++ b/library/util_gmii_to_rgmii/mdc_mdio.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v index 5ff964aa3..8c542b92a 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_hbm/util_hbm.v b/library/util_hbm/util_hbm.v index 055be7211..55803e8c5 100644 --- a/library/util_hbm/util_hbm.v +++ b/library/util_hbm/util_hbm.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_mfifo/util_mfifo.v b/library/util_mfifo/util_mfifo.v index 4e0fc6165..0d9acffc3 100644 --- a/library/util_mfifo/util_mfifo.v +++ b/library/util_mfifo/util_mfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_mii_to_rmii/mac_phy_link.v b/library/util_mii_to_rmii/mac_phy_link.v index 9aca343b1..5a9e5481d 100644 --- a/library/util_mii_to_rmii/mac_phy_link.v +++ b/library/util_mii_to_rmii/mac_phy_link.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_mii_to_rmii/phy_mac_link.v b/library/util_mii_to_rmii/phy_mac_link.v index bc028fd37..599302ae3 100644 --- a/library/util_mii_to_rmii/phy_mac_link.v +++ b/library/util_mii_to_rmii/phy_mac_link.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_mii_to_rmii/util_mii_to_rmii.v b/library/util_mii_to_rmii/util_mii_to_rmii.v index 4d7301fc9..59fca8264 100644 --- a/library/util_mii_to_rmii/util_mii_to_rmii.v +++ b/library/util_mii_to_rmii/util_mii_to_rmii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_pack/tb/cpack_tb.v b/library/util_pack/tb/cpack_tb.v index 8279510f3..3d7e00598 100644 --- a/library/util_pack/tb/cpack_tb.v +++ b/library/util_pack/tb/cpack_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/tb/tb_base.v b/library/util_pack/tb/tb_base.v index f721d873d..169b98f83 100644 --- a/library/util_pack/tb/tb_base.v +++ b/library/util_pack/tb/tb_base.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/tb/underflow_tb.v b/library/util_pack/tb/underflow_tb.v index a214b86bf..c4b15abaa 100644 --- a/library/util_pack/tb/underflow_tb.v +++ b/library/util_pack/tb/underflow_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/tb/upack_tb.v b/library/util_pack/tb/upack_tb.v index aab311435..cc455c248 100644 --- a/library/util_pack/tb/upack_tb.v +++ b/library/util_pack/tb/upack_tb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/util_cpack2/util_cpack2.v b/library/util_pack/util_cpack2/util_cpack2.v index 1f604f2f2..8006a2493 100644 --- a/library/util_pack/util_cpack2/util_cpack2.v +++ b/library/util_pack/util_cpack2/util_cpack2.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/util_cpack2/util_cpack2_impl.v b/library/util_pack/util_cpack2/util_cpack2_impl.v index 3d621eb1c..0b7b7530f 100644 --- a/library/util_pack/util_cpack2/util_cpack2_impl.v +++ b/library/util_pack/util_cpack2/util_cpack2_impl.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/util_pack_common/pack_ctrl.v b/library/util_pack/util_pack_common/pack_ctrl.v index 1966bf9eb..d4df07d79 100644 --- a/library/util_pack/util_pack_common/pack_ctrl.v +++ b/library/util_pack/util_pack_common/pack_ctrl.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/util_pack_common/pack_interconnect.v b/library/util_pack/util_pack_common/pack_interconnect.v index d3ba07e12..273b76ce3 100644 --- a/library/util_pack/util_pack_common/pack_interconnect.v +++ b/library/util_pack/util_pack_common/pack_interconnect.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/util_pack_common/pack_network.v b/library/util_pack/util_pack_common/pack_network.v index 20ff2d516..6547a6c0f 100644 --- a/library/util_pack/util_pack_common/pack_network.v +++ b/library/util_pack/util_pack_common/pack_network.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/util_pack_common/pack_shell.v b/library/util_pack/util_pack_common/pack_shell.v index be48c6900..3a236dc9a 100644 --- a/library/util_pack/util_pack_common/pack_shell.v +++ b/library/util_pack/util_pack_common/pack_shell.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/util_upack2/util_upack2.v b/library/util_pack/util_upack2/util_upack2.v index e0523470a..3c53e7457 100644 --- a/library/util_pack/util_upack2/util_upack2.v +++ b/library/util_pack/util_upack2/util_upack2.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pack/util_upack2/util_upack2_impl.v b/library/util_pack/util_upack2/util_upack2_impl.v index 836426067..395a76fa0 100644 --- a/library/util_pack/util_upack2/util_upack2_impl.v +++ b/library/util_pack/util_upack2/util_upack2_impl.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/library/util_pad/util_pad.v b/library/util_pad/util_pad.v index 5c48781d0..c3bd5b84a 100644 --- a/library/util_pad/util_pad.v +++ b/library/util_pad/util_pad.v @@ -1,22 +1,34 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // -// Each core or library found in this collection may have its own licensing terms. -// The user should keep this in in mind while exploring these cores. +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. // -// Redistribution and use in source and binary forms, -// with or without modification of this file, are permitted under the terms of either -// (at the option of the user): +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory, or at: -// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// // // OR // -// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: -// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v index 4fa0ed3c8..608f5e757 100644 --- a/library/util_rfifo/util_rfifo.v +++ b/library/util_rfifo/util_rfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi.v b/library/util_sigma_delta_spi/util_sigma_delta_spi.v index d0454163b..e9ea123e1 100644 --- a/library/util_sigma_delta_spi/util_sigma_delta_spi.v +++ b/library/util_sigma_delta_spi/util_sigma_delta_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_tdd_sync/util_tdd_sync.v b/library/util_tdd_sync/util_tdd_sync.v index fc708872c..9fd3aa579 100644 --- a/library/util_tdd_sync/util_tdd_sync.v +++ b/library/util_tdd_sync/util_tdd_sync.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_var_fifo/util_var_fifo.v b/library/util_var_fifo/util_var_fifo.v index 57d00506b..19fd7cb89 100644 --- a/library/util_var_fifo/util_var_fifo.v +++ b/library/util_var_fifo/util_var_fifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v index c74f0584f..a6dbb7c10 100644 --- a/library/util_wfifo/util_wfifo.v +++ b/library/util_wfifo/util_wfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo.v b/library/xilinx/axi_adcfifo/axi_adcfifo.v index e6a858eb1..628b3e39a 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v b/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v index a5191f664..386b48495 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v b/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v index 101023f64..9b13e49b0 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v b/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v index 7aa23b24e..bb4881c60 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v b/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v index 01695f935..cd1d2200c 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v index 27f209041..58ca84090 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_es.v b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v index 78a042a3d..1dd81b3d9 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_es.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v b/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v index 74a04492f..b705dfa64 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v b/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v index 389a79fd2..325be6bed 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v index 213e6e467..3ac801e0a 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v index 2fea95bcb..ad5f56659 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v b/library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v index a1499dfdd..aed1457c2 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v index 969568c3b..549f1a046 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v index 0756bae43..66bb6b4b9 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v index dccbb8163..befefe16b 100644 --- a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v index 90ba52db8..e23dd973d 100644 --- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_data_clk.v b/library/xilinx/common/ad_data_clk.v index ffcac984b..08ac184dc 100644 --- a/library/xilinx/common/ad_data_clk.v +++ b/library/xilinx/common/ad_data_clk.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_data_in.v b/library/xilinx/common/ad_data_in.v index 07b9b5dd9..090faf0c6 100755 --- a/library/xilinx/common/ad_data_in.v +++ b/library/xilinx/common/ad_data_in.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_data_out.v b/library/xilinx/common/ad_data_out.v index b1f4c3e3f..68cd566d9 100755 --- a/library/xilinx/common/ad_data_out.v +++ b/library/xilinx/common/ad_data_out.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_dcfilter.v b/library/xilinx/common/ad_dcfilter.v index de853a928..c05b83aac 100644 --- a/library/xilinx/common/ad_dcfilter.v +++ b/library/xilinx/common/ad_dcfilter.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_mmcm_drp.v b/library/xilinx/common/ad_mmcm_drp.v index 86acf8584..bf19b4f21 100644 --- a/library/xilinx/common/ad_mmcm_drp.v +++ b/library/xilinx/common/ad_mmcm_drp.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_mul.v b/library/xilinx/common/ad_mul.v index 30f38b6e3..aeaac430b 100644 --- a/library/xilinx/common/ad_mul.v +++ b/library/xilinx/common/ad_mul.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v index c9e39b436..c438ac3bc 100644 --- a/library/xilinx/common/ad_serdes_clk.v +++ b/library/xilinx/common/ad_serdes_clk.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v index f483108bb..b9218b6de 100644 --- a/library/xilinx/common/ad_serdes_in.v +++ b/library/xilinx/common/ad_serdes_in.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v index 3e5322234..a8d44716d 100644 --- a/library/xilinx/common/ad_serdes_out.v +++ b/library/xilinx/common/ad_serdes_out.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v index 70abfa3a5..ee127ba95 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr.v +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v index f05c05361..7f71c52e2 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v index ece8276ad..7b95fc542 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/xilinx/util_clkdiv/util_clkdiv.v b/library/xilinx/util_clkdiv/util_clkdiv.v index 4864ef0fc..e1930e027 100644 --- a/library/xilinx/util_clkdiv/util_clkdiv.v +++ b/library/xilinx/util_clkdiv/util_clkdiv.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad40xx_fmc/zed/system_top_ad40xx.v b/projects/ad40xx_fmc/zed/system_top_ad40xx.v index d031ce6cf..b3e11e620 100644 --- a/projects/ad40xx_fmc/zed/system_top_ad40xx.v +++ b/projects/ad40xx_fmc/zed/system_top_ad40xx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad40xx_fmc/zed/system_top_adaq400x.v b/projects/ad40xx_fmc/zed/system_top_adaq400x.v index f22e39bd1..e8a8973b5 100644 --- a/projects/ad40xx_fmc/zed/system_top_adaq400x.v +++ b/projects/ad40xx_fmc/zed/system_top_adaq400x.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad4110/zed/system_top.v b/projects/ad4110/zed/system_top.v index ba21d63f0..0cc546668 100644 --- a/projects/ad4110/zed/system_top.v +++ b/projects/ad4110/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad4134_fmc/zed/system_top.v b/projects/ad4134_fmc/zed/system_top.v index 6d20e2406..1a1c2c8a9 100755 --- a/projects/ad4134_fmc/zed/system_top.v +++ b/projects/ad4134_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad4630_fmc/zed/system_top.v b/projects/ad4630_fmc/zed/system_top.v index 3ab272255..7b68f4aad 100644 --- a/projects/ad4630_fmc/zed/system_top.v +++ b/projects/ad4630_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad469x_fmc/zed/system_top.v b/projects/ad469x_fmc/zed/system_top.v index 5f5f97efe..bacee6e1f 100644 --- a/projects/ad469x_fmc/zed/system_top.v +++ b/projects/ad469x_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad5758_sdz/zed/system_top.v b/projects/ad5758_sdz/zed/system_top.v index e86e4208d..5fc9dab64 100644 --- a/projects/ad5758_sdz/zed/system_top.v +++ b/projects/ad5758_sdz/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad5766_sdz/zed/system_top.v b/projects/ad5766_sdz/zed/system_top.v index c05eea862..134e04d74 100644 --- a/projects/ad5766_sdz/zed/system_top.v +++ b/projects/ad5766_sdz/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v index f81efb206..7d2858e82 100644 --- a/projects/ad6676evb/vc707/system_top.v +++ b/projects/ad6676evb/vc707/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v index 693e32b7a..c7d197bf8 100644 --- a/projects/ad6676evb/zc706/system_top.v +++ b/projects/ad6676evb/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad7134_fmc/zed/system_top.v b/projects/ad7134_fmc/zed/system_top.v index a38144136..47e266236 100644 --- a/projects/ad7134_fmc/zed/system_top.v +++ b/projects/ad7134_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad719x_asdz/coraz7s/system_top.v b/projects/ad719x_asdz/coraz7s/system_top.v index eb708d8a2..82663623d 100644 --- a/projects/ad719x_asdz/coraz7s/system_top.v +++ b/projects/ad719x_asdz/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad738x_fmc/zed/system_top.v b/projects/ad738x_fmc/zed/system_top.v index 3b5463549..72de92fe9 100644 --- a/projects/ad738x_fmc/zed/system_top.v +++ b/projects/ad738x_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad7405_fmc/zed/system_top_differential.v b/projects/ad7405_fmc/zed/system_top_differential.v index 79ed61c1c..d822dde9e 100644 --- a/projects/ad7405_fmc/zed/system_top_differential.v +++ b/projects/ad7405_fmc/zed/system_top_differential.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad7405_fmc/zed/system_top_singlended.v b/projects/ad7405_fmc/zed/system_top_singlended.v index e6fd6dc34..2cabf4196 100644 --- a/projects/ad7405_fmc/zed/system_top_singlended.v +++ b/projects/ad7405_fmc/zed/system_top_singlended.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad7606x_fmc/zed/system_top.v b/projects/ad7606x_fmc/zed/system_top.v index 717d2c6b0..851675b5e 100644 --- a/projects/ad7606x_fmc/zed/system_top.v +++ b/projects/ad7606x_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v index d12861e9f..6de7fae26 100644 --- a/projects/ad7616_sdz/zc706/system_top_pi.v +++ b/projects/ad7616_sdz/zc706/system_top_pi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad7616_sdz/zc706/system_top_si.v b/projects/ad7616_sdz/zc706/system_top_si.v index 0a79d59b0..9f7ef0209 100644 --- a/projects/ad7616_sdz/zc706/system_top_si.v +++ b/projects/ad7616_sdz/zc706/system_top_si.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v index 53944dd89..91a16f3e3 100644 --- a/projects/ad7616_sdz/zed/system_top_pi.v +++ b/projects/ad7616_sdz/zed/system_top_pi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad7616_sdz/zed/system_top_si.v b/projects/ad7616_sdz/zed/system_top_si.v index baf371cfe..62d98150c 100644 --- a/projects/ad7616_sdz/zed/system_top_si.v +++ b/projects/ad7616_sdz/zed/system_top_si.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad77681evb/zed/system_top.v b/projects/ad77681evb/zed/system_top.v index 5de78334a..5aef20f81 100644 --- a/projects/ad77681evb/zed/system_top.v +++ b/projects/ad77681evb/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad7768evb/zed/system_top.v b/projects/ad7768evb/zed/system_top.v index 49913da85..17c593817 100644 --- a/projects/ad7768evb/zed/system_top.v +++ b/projects/ad7768evb/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad777x_ardz/de10nano/system_top.v b/projects/ad777x_ardz/de10nano/system_top.v index 9639c9694..2b869d48a 100644 --- a/projects/ad777x_ardz/de10nano/system_top.v +++ b/projects/ad777x_ardz/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/ad777x_ardz/zed/system_top.v b/projects/ad777x_ardz/zed/system_top.v index 753754950..56f6bfdc5 100644 --- a/projects/ad777x_ardz/zed/system_top.v +++ b/projects/ad777x_ardz/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9081_fmca_ebz/a10soc/system_top.v b/projects/ad9081_fmca_ebz/a10soc/system_top.v index abcc0159b..b11f5f031 100755 --- a/projects/ad9081_fmca_ebz/a10soc/system_top.v +++ b/projects/ad9081_fmca_ebz/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9081_fmca_ebz/vck190/system_top.v b/projects/ad9081_fmca_ebz/vck190/system_top.v index b741463d9..7ca5fae56 100644 --- a/projects/ad9081_fmca_ebz/vck190/system_top.v +++ b/projects/ad9081_fmca_ebz/vck190/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9081_fmca_ebz/vcu118/system_top.v b/projects/ad9081_fmca_ebz/vcu118/system_top.v index 66c505405..5e50f647d 100644 --- a/projects/ad9081_fmca_ebz/vcu118/system_top.v +++ b/projects/ad9081_fmca_ebz/vcu118/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9081_fmca_ebz/vcu128/system_top.v b/projects/ad9081_fmca_ebz/vcu128/system_top.v index 008184c39..fe2fe3feb 100644 --- a/projects/ad9081_fmca_ebz/vcu128/system_top.v +++ b/projects/ad9081_fmca_ebz/vcu128/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9081_fmca_ebz/zc706/system_top.v b/projects/ad9081_fmca_ebz/zc706/system_top.v index 45922f5b2..707c3b14c 100644 --- a/projects/ad9081_fmca_ebz/zc706/system_top.v +++ b/projects/ad9081_fmca_ebz/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9081_fmca_ebz/zcu102/system_top.v b/projects/ad9081_fmca_ebz/zcu102/system_top.v index a5c84d77a..8b1693f28 100644 --- a/projects/ad9081_fmca_ebz/zcu102/system_top.v +++ b/projects/ad9081_fmca_ebz/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9081_fmca_ebz_x_band/zcu102/system_top.v b/projects/ad9081_fmca_ebz_x_band/zcu102/system_top.v index 77c3c7990..b9ffc5a1d 100644 --- a/projects/ad9081_fmca_ebz_x_band/zcu102/system_top.v +++ b/projects/ad9081_fmca_ebz_x_band/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9083_evb/a10soc/system_top.v b/projects/ad9083_evb/a10soc/system_top.v index 43fa61e9b..16ca9a402 100644 --- a/projects/ad9083_evb/a10soc/system_top.v +++ b/projects/ad9083_evb/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9083_evb/zcu102/system_top.v b/projects/ad9083_evb/zcu102/system_top.v index 17eb84faa..71f4b6ba1 100644 --- a/projects/ad9083_evb/zcu102/system_top.v +++ b/projects/ad9083_evb/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9083_vna/zcu102/system_top.v b/projects/ad9083_vna/zcu102/system_top.v index c2f5cacb7..91b266d66 100644 --- a/projects/ad9083_vna/zcu102/system_top.v +++ b/projects/ad9083_vna/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9208_dual_ebz/vcu118/system_top.v b/projects/ad9208_dual_ebz/vcu118/system_top.v index fa4194702..26fed4214 100644 --- a/projects/ad9208_dual_ebz/vcu118/system_top.v +++ b/projects/ad9208_dual_ebz/vcu118/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9209_fmca_ebz/vck190/system_top.v b/projects/ad9209_fmca_ebz/vck190/system_top.v index bf70f3753..2f059689a 100644 --- a/projects/ad9209_fmca_ebz/vck190/system_top.v +++ b/projects/ad9209_fmca_ebz/vck190/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9213_dual_ebz/s10soc/system_top.v b/projects/ad9213_dual_ebz/s10soc/system_top.v index 207c6ca99..5f0547825 100755 --- a/projects/ad9213_dual_ebz/s10soc/system_top.v +++ b/projects/ad9213_dual_ebz/s10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9265_fmc/common/ad9265_spi.v b/projects/ad9265_fmc/common/ad9265_spi.v index a68115ba2..06cddd090 100644 --- a/projects/ad9265_fmc/common/ad9265_spi.v +++ b/projects/ad9265_fmc/common/ad9265_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9265_fmc/zc706/system_top.v b/projects/ad9265_fmc/zc706/system_top.v index a935ac4aa..854c993e4 100644 --- a/projects/ad9265_fmc/zc706/system_top.v +++ b/projects/ad9265_fmc/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9434_fmc/common/ad9434_spi.v b/projects/ad9434_fmc/common/ad9434_spi.v index cede23808..b59de38b9 100644 --- a/projects/ad9434_fmc/common/ad9434_spi.v +++ b/projects/ad9434_fmc/common/ad9434_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9434_fmc/zc706/system_top.v b/projects/ad9434_fmc/zc706/system_top.v index 73e5a7bee..4e22f121d 100644 --- a/projects/ad9434_fmc/zc706/system_top.v +++ b/projects/ad9434_fmc/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9467_fmc/common/ad9467_spi.v b/projects/ad9467_fmc/common/ad9467_spi.v index 15bc3b4d4..6fc854929 100644 --- a/projects/ad9467_fmc/common/ad9467_spi.v +++ b/projects/ad9467_fmc/common/ad9467_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9467_fmc/kc705/system_top.v b/projects/ad9467_fmc/kc705/system_top.v index 56b965a27..599d18819 100644 --- a/projects/ad9467_fmc/kc705/system_top.v +++ b/projects/ad9467_fmc/kc705/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9467_fmc/zed/system_top.v b/projects/ad9467_fmc/zed/system_top.v index 8110828ec..876f76561 100644 --- a/projects/ad9467_fmc/zed/system_top.v +++ b/projects/ad9467_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9656_fmc/zcu102/system_top.v b/projects/ad9656_fmc/zcu102/system_top.v index 4463c8469..9f1fa59f7 100644 --- a/projects/ad9656_fmc/zcu102/system_top.v +++ b/projects/ad9656_fmc/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9695_fmc/zcu102/system_top.v b/projects/ad9695_fmc/zcu102/system_top.v index a530db125..99a3f4149 100644 --- a/projects/ad9695_fmc/zcu102/system_top.v +++ b/projects/ad9695_fmc/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9739a_fmc/zc706/system_top.v b/projects/ad9739a_fmc/zc706/system_top.v index 5d8f35468..58b90cd09 100644 --- a/projects/ad9739a_fmc/zc706/system_top.v +++ b/projects/ad9739a_fmc/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad9783_ebz/zcu102/system_top.v b/projects/ad9783_ebz/zcu102/system_top.v index 70526be07..0fbea80bc 100755 --- a/projects/ad9783_ebz/zcu102/system_top.v +++ b/projects/ad9783_ebz/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad_fmclidar1_ebz/a10soc/system_top.v b/projects/ad_fmclidar1_ebz/a10soc/system_top.v index bb97427ee..3581b4fdf 100644 --- a/projects/ad_fmclidar1_ebz/a10soc/system_top.v +++ b/projects/ad_fmclidar1_ebz/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v b/projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v index e804a01cf..69dbc61ba 100644 --- a/projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v +++ b/projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad_fmclidar1_ebz/common/util_tia_chsel.v b/projects/ad_fmclidar1_ebz/common/util_tia_chsel.v index 6eb83e990..49ace5664 100644 --- a/projects/ad_fmclidar1_ebz/common/util_tia_chsel.v +++ b/projects/ad_fmclidar1_ebz/common/util_tia_chsel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad_fmclidar1_ebz/zc706/system_top.v b/projects/ad_fmclidar1_ebz/zc706/system_top.v index 004532c21..bf34c1bf3 100644 --- a/projects/ad_fmclidar1_ebz/zc706/system_top.v +++ b/projects/ad_fmclidar1_ebz/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad_fmclidar1_ebz/zcu102/system_top.v b/projects/ad_fmclidar1_ebz/zcu102/system_top.v index 13097db12..be5a20e12 100644 --- a/projects/ad_fmclidar1_ebz/zcu102/system_top.v +++ b/projects/ad_fmclidar1_ebz/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad_quadmxfe1_ebz/common/quad_mxfe_gpio_mux.v b/projects/ad_quadmxfe1_ebz/common/quad_mxfe_gpio_mux.v index 0b87fc489..5c245e819 100644 --- a/projects/ad_quadmxfe1_ebz/common/quad_mxfe_gpio_mux.v +++ b/projects/ad_quadmxfe1_ebz/common/quad_mxfe_gpio_mux.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/ad_quadmxfe1_ebz/vcu118/system_top.v b/projects/ad_quadmxfe1_ebz/vcu118/system_top.v index 7070d8306..1bcddc732 100644 --- a/projects/ad_quadmxfe1_ebz/vcu118/system_top.v +++ b/projects/ad_quadmxfe1_ebz/vcu118/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adaq7980_sdz/zed/system_top.v b/projects/adaq7980_sdz/zed/system_top.v index eacf056d7..55943c2d6 100644 --- a/projects/adaq7980_sdz/zed/system_top.v +++ b/projects/adaq7980_sdz/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adaq8092_fmc/zed/system_top.v b/projects/adaq8092_fmc/zed/system_top.v index 7a82db6c4..b38ebf068 100644 --- a/projects/adaq8092_fmc/zed/system_top.v +++ b/projects/adaq8092_fmc/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9001/a10soc/system_top.v b/projects/adrv9001/a10soc/system_top.v index 2d37f2919..aa7f00d8e 100644 --- a/projects/adrv9001/a10soc/system_top.v +++ b/projects/adrv9001/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9001/zc706/system_top.v b/projects/adrv9001/zc706/system_top.v index 009bd1477..c48565373 100644 --- a/projects/adrv9001/zc706/system_top.v +++ b/projects/adrv9001/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9001/zcu102/system_top.v b/projects/adrv9001/zcu102/system_top.v index da0bf6e6e..6bf27d6ed 100644 --- a/projects/adrv9001/zcu102/system_top.v +++ b/projects/adrv9001/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9001/zed/system_top.v b/projects/adrv9001/zed/system_top.v index 9a1e45907..b88605b2c 100644 --- a/projects/adrv9001/zed/system_top.v +++ b/projects/adrv9001/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9009/a10soc/system_top.v b/projects/adrv9009/a10soc/system_top.v index 5681ddfa8..84f05f3c7 100755 --- a/projects/adrv9009/a10soc/system_top.v +++ b/projects/adrv9009/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9009/s10soc/system_top.v b/projects/adrv9009/s10soc/system_top.v index 3a255a6dc..c4bec2467 100755 --- a/projects/adrv9009/s10soc/system_top.v +++ b/projects/adrv9009/s10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9009/zc706/system_top.v b/projects/adrv9009/zc706/system_top.v index b93e2f5b4..8c1f94373 100644 --- a/projects/adrv9009/zc706/system_top.v +++ b/projects/adrv9009/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9009/zcu102/system_top.v b/projects/adrv9009/zcu102/system_top.v index 8bcabc5b4..bb7e37bbc 100644 --- a/projects/adrv9009/zcu102/system_top.v +++ b/projects/adrv9009/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v b/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v index dd2774b44..784718008 100644 --- a/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_top.v b/projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_top.v index 810ef5033..ab1fdfb7f 100644 --- a/projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_top.v +++ b/projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_top.v b/projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_top.v index ff5fc1ab8..d21b50f68 100755 --- a/projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_top.v +++ b/projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/adrv9009zu11eg/adrv2crr_xmicrowave/system_top.v b/projects/adrv9009zu11eg/adrv2crr_xmicrowave/system_top.v index d0c572d23..ee72be7fa 100755 --- a/projects/adrv9009zu11eg/adrv2crr_xmicrowave/system_top.v +++ b/projects/adrv9009zu11eg/adrv2crr_xmicrowave/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/adrv9009zu11eg/common/adrv9009zu11eg_spi.v b/projects/adrv9009zu11eg/common/adrv9009zu11eg_spi.v index 41df61fa1..53d62f998 100644 --- a/projects/adrv9009zu11eg/common/adrv9009zu11eg_spi.v +++ b/projects/adrv9009zu11eg/common/adrv9009zu11eg_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9361z7035/ccbob_cmos/system_top.v b/projects/adrv9361z7035/ccbob_cmos/system_top.v index 5e3b6a87b..551e3d109 100644 --- a/projects/adrv9361z7035/ccbob_cmos/system_top.v +++ b/projects/adrv9361z7035/ccbob_cmos/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9361z7035/ccbob_lvds/system_top.v b/projects/adrv9361z7035/ccbob_lvds/system_top.v index 7317be34a..114706e8b 100644 --- a/projects/adrv9361z7035/ccbob_lvds/system_top.v +++ b/projects/adrv9361z7035/ccbob_lvds/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9361z7035/ccfmc_lvds/system_top.v b/projects/adrv9361z7035/ccfmc_lvds/system_top.v index 8af22cb2f..14bc65282 100644 --- a/projects/adrv9361z7035/ccfmc_lvds/system_top.v +++ b/projects/adrv9361z7035/ccfmc_lvds/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9361z7035/ccpackrf_lvds/system_top.v b/projects/adrv9361z7035/ccpackrf_lvds/system_top.v index 6e7391541..5a2f7db00 100644 --- a/projects/adrv9361z7035/ccpackrf_lvds/system_top.v +++ b/projects/adrv9361z7035/ccpackrf_lvds/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9364z7020/ccbob_cmos/system_top.v b/projects/adrv9364z7020/ccbob_cmos/system_top.v index cb5c65d82..2daf5b774 100644 --- a/projects/adrv9364z7020/ccbob_cmos/system_top.v +++ b/projects/adrv9364z7020/ccbob_cmos/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9364z7020/ccbob_lvds/system_top.v b/projects/adrv9364z7020/ccbob_lvds/system_top.v index eb35fbeb4..e2e5e39bb 100644 --- a/projects/adrv9364z7020/ccbob_lvds/system_top.v +++ b/projects/adrv9364z7020/ccbob_lvds/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9364z7020/ccpackrf_lvds/system_top.v b/projects/adrv9364z7020/ccpackrf_lvds/system_top.v index 09cbe65df..1d9df728c 100644 --- a/projects/adrv9364z7020/ccpackrf_lvds/system_top.v +++ b/projects/adrv9364z7020/ccpackrf_lvds/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v index d2a900f3c..b9ad32465 100644 --- a/projects/adrv9371x/a10soc/system_top.v +++ b/projects/adrv9371x/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9371x/kcu105/system_top.v b/projects/adrv9371x/kcu105/system_top.v index 99d379dc3..5581808a9 100644 --- a/projects/adrv9371x/kcu105/system_top.v +++ b/projects/adrv9371x/kcu105/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9371x/zc706/system_top.v b/projects/adrv9371x/zc706/system_top.v index 3bc4e70f9..2bd63dc41 100644 --- a/projects/adrv9371x/zc706/system_top.v +++ b/projects/adrv9371x/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adrv9371x/zcu102/system_top.v b/projects/adrv9371x/zcu102/system_top.v index 76f6fd877..a1aff419c 100644 --- a/projects/adrv9371x/zcu102/system_top.v +++ b/projects/adrv9371x/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adv7511/zc702/system_top.v b/projects/adv7511/zc702/system_top.v index 86dbc6ee7..16637fb60 100644 --- a/projects/adv7511/zc702/system_top.v +++ b/projects/adv7511/zc702/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adv7511/zc706/system_top.v b/projects/adv7511/zc706/system_top.v index ada288847..537d318d1 100644 --- a/projects/adv7511/zc706/system_top.v +++ b/projects/adv7511/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adv7511/zed/system_top.v b/projects/adv7511/zed/system_top.v index fecb74780..ba26af609 100644 --- a/projects/adv7511/zed/system_top.v +++ b/projects/adv7511/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/adv7513/de10nano/system_top.v b/projects/adv7513/de10nano/system_top.v index 6eb751f10..41fefdf87 100644 --- a/projects/adv7513/de10nano/system_top.v +++ b/projects/adv7513/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2019 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/arradio/c5soc/system_top.v b/projects/arradio/c5soc/system_top.v index 6b6e5b8de..68064c52d 100644 --- a/projects/arradio/c5soc/system_top.v +++ b/projects/arradio/c5soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0363/zed/system_top.v b/projects/cn0363/zed/system_top.v index 1e5139652..fe8585e18 100644 --- a/projects/cn0363/zed/system_top.v +++ b/projects/cn0363/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0501/coraz7s/system_top.v b/projects/cn0501/coraz7s/system_top.v index 5e1bec5ed..93499068a 100644 --- a/projects/cn0501/coraz7s/system_top.v +++ b/projects/cn0501/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/a10soc/system_top.v b/projects/cn0506/a10soc/system_top.v index 532fd8571..394b21181 100644 --- a/projects/cn0506/a10soc/system_top.v +++ b/projects/cn0506/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zc706/system_top_mii.v b/projects/cn0506/zc706/system_top_mii.v index 634c96cde..bc89da51b 100644 --- a/projects/cn0506/zc706/system_top_mii.v +++ b/projects/cn0506/zc706/system_top_mii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zc706/system_top_rgmii.v b/projects/cn0506/zc706/system_top_rgmii.v index c94b5a8de..f63dc3d07 100644 --- a/projects/cn0506/zc706/system_top_rgmii.v +++ b/projects/cn0506/zc706/system_top_rgmii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zc706/system_top_rmii.v b/projects/cn0506/zc706/system_top_rmii.v index a61dbebff..1f6d77f1e 100644 --- a/projects/cn0506/zc706/system_top_rmii.v +++ b/projects/cn0506/zc706/system_top_rmii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zcu102/system_top_mii.v b/projects/cn0506/zcu102/system_top_mii.v index d1fec2074..dcd2c6b95 100644 --- a/projects/cn0506/zcu102/system_top_mii.v +++ b/projects/cn0506/zcu102/system_top_mii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zcu102/system_top_rgmii.v b/projects/cn0506/zcu102/system_top_rgmii.v index 313d63b7e..e13bbe677 100644 --- a/projects/cn0506/zcu102/system_top_rgmii.v +++ b/projects/cn0506/zcu102/system_top_rgmii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zcu102/system_top_rmii.v b/projects/cn0506/zcu102/system_top_rmii.v index a829be69f..3ae1b5224 100644 --- a/projects/cn0506/zcu102/system_top_rmii.v +++ b/projects/cn0506/zcu102/system_top_rmii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zed/system_top_mii.v b/projects/cn0506/zed/system_top_mii.v index 4aa95d532..e686693c2 100644 --- a/projects/cn0506/zed/system_top_mii.v +++ b/projects/cn0506/zed/system_top_mii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zed/system_top_rgmii.v b/projects/cn0506/zed/system_top_rgmii.v index 529708be1..82413319a 100644 --- a/projects/cn0506/zed/system_top_rgmii.v +++ b/projects/cn0506/zed/system_top_rgmii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0506/zed/system_top_rmii.v b/projects/cn0506/zed/system_top_rmii.v index 07eda837e..5812cbfc8 100644 --- a/projects/cn0506/zed/system_top_rmii.v +++ b/projects/cn0506/zed/system_top_rmii.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0540/coraz7s/system_top.v b/projects/cn0540/coraz7s/system_top.v index 306376c3f..a4a0b7a4c 100755 --- a/projects/cn0540/coraz7s/system_top.v +++ b/projects/cn0540/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2019 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0540/de10nano/system_top.v b/projects/cn0540/de10nano/system_top.v index 664c9d497..57b64f630 100755 --- a/projects/cn0540/de10nano/system_top.v +++ b/projects/cn0540/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0561/coraz7s/system_top.v b/projects/cn0561/coraz7s/system_top.v index 949d4ef58..d63106dd2 100644 --- a/projects/cn0561/coraz7s/system_top.v +++ b/projects/cn0561/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2019 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0561/de10nano/system_top.v b/projects/cn0561/de10nano/system_top.v index b834d96d0..2c8b23b0f 100644 --- a/projects/cn0561/de10nano/system_top.v +++ b/projects/cn0561/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0561/zed/system_top.v b/projects/cn0561/zed/system_top.v index 95da353c5..27cad7542 100755 --- a/projects/cn0561/zed/system_top.v +++ b/projects/cn0561/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0577/zed/system_top.v b/projects/cn0577/zed/system_top.v index ba5943653..b65b10223 100644 --- a/projects/cn0577/zed/system_top.v +++ b/projects/cn0577/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0579/coraz7s/system_top.v b/projects/cn0579/coraz7s/system_top.v index 8c636ce30..da12fe7ce 100644 --- a/projects/cn0579/coraz7s/system_top.v +++ b/projects/cn0579/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/cn0579/de10nano/system_top.v b/projects/cn0579/de10nano/system_top.v index ae1a181af..7cefaf24a 100644 --- a/projects/cn0579/de10nano/system_top.v +++ b/projects/cn0579/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/common/a10gx/system_top.v b/projects/common/a10gx/system_top.v index 03b345798..b89baef41 100755 --- a/projects/common/a10gx/system_top.v +++ b/projects/common/a10gx/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/a10soc/system_top.v b/projects/common/a10soc/system_top.v index 480069713..f5bcd9638 100755 --- a/projects/common/a10soc/system_top.v +++ b/projects/common/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/ac701/system_top.v b/projects/common/ac701/system_top.v index bb5b5a125..bc551cbd1 100755 --- a/projects/common/ac701/system_top.v +++ b/projects/common/ac701/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2011 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/c5soc/system_top.v b/projects/common/c5soc/system_top.v index e2d3fe5c6..66e3dbaa1 100755 --- a/projects/common/c5soc/system_top.v +++ b/projects/common/c5soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/coraz7s/system_top.v b/projects/common/coraz7s/system_top.v index 52722a108..fe7ec5255 100755 --- a/projects/common/coraz7s/system_top.v +++ b/projects/common/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/common/de10nano/system_top.v b/projects/common/de10nano/system_top.v index 9a587d8e2..34e85db67 100644 --- a/projects/common/de10nano/system_top.v +++ b/projects/common/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2019 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/common/kc705/system_top.v b/projects/common/kc705/system_top.v index 5cdcf4526..28b207c2f 100755 --- a/projects/common/kc705/system_top.v +++ b/projects/common/kc705/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/kcu105/system_top.v b/projects/common/kcu105/system_top.v index dbf97aa5b..6c60f5288 100755 --- a/projects/common/kcu105/system_top.v +++ b/projects/common/kcu105/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/kv260/system_top.v b/projects/common/kv260/system_top.v index dd3a6c097..383830f99 100644 --- a/projects/common/kv260/system_top.v +++ b/projects/common/kv260/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/s10soc/system_top.v b/projects/common/s10soc/system_top.v index e500579c9..b86c9f84f 100755 --- a/projects/common/s10soc/system_top.v +++ b/projects/common/s10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/vc707/system_top.v b/projects/common/vc707/system_top.v index c9c6b6eea..b20490f1c 100755 --- a/projects/common/vc707/system_top.v +++ b/projects/common/vc707/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/vc709/system_top.v b/projects/common/vc709/system_top.v index 610b3f464..a9193c3ff 100755 --- a/projects/common/vc709/system_top.v +++ b/projects/common/vc709/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/vck190/system_top.v b/projects/common/vck190/system_top.v index bb8f9bc1c..3a7b3eaa6 100755 --- a/projects/common/vck190/system_top.v +++ b/projects/common/vck190/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/vcu118/system_top.v b/projects/common/vcu118/system_top.v index c92846f69..874dcf287 100755 --- a/projects/common/vcu118/system_top.v +++ b/projects/common/vcu118/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/vcu128/system_top.v b/projects/common/vcu128/system_top.v index 82aff5103..43c2dc860 100755 --- a/projects/common/vcu128/system_top.v +++ b/projects/common/vcu128/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/vmk180/system_top.v b/projects/common/vmk180/system_top.v index bb8f9bc1c..3a7b3eaa6 100755 --- a/projects/common/vmk180/system_top.v +++ b/projects/common/vmk180/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/zc702/system_top.v b/projects/common/zc702/system_top.v index 163a6debc..02e209af1 100755 --- a/projects/common/zc702/system_top.v +++ b/projects/common/zc702/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/zc706/system_top.v b/projects/common/zc706/system_top.v index 6bd4ca388..52c4e1e5b 100755 --- a/projects/common/zc706/system_top.v +++ b/projects/common/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/zcu102/system_top.v b/projects/common/zcu102/system_top.v index 4f75ef53a..495a1b1c5 100755 --- a/projects/common/zcu102/system_top.v +++ b/projects/common/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/common/zed/system_top.v b/projects/common/zed/system_top.v index fa89d1319..2843a89b6 100755 --- a/projects/common/zed/system_top.v +++ b/projects/common/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/dac_fmc_ebz/a10soc/system_top.v b/projects/dac_fmc_ebz/a10soc/system_top.v index f7fe226d2..73962ef33 100644 --- a/projects/dac_fmc_ebz/a10soc/system_top.v +++ b/projects/dac_fmc_ebz/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/dac_fmc_ebz/vcu118/system_top.v b/projects/dac_fmc_ebz/vcu118/system_top.v index 7b0eda624..3d4e021a1 100755 --- a/projects/dac_fmc_ebz/vcu118/system_top.v +++ b/projects/dac_fmc_ebz/vcu118/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/dac_fmc_ebz/zc706/system_top.v b/projects/dac_fmc_ebz/zc706/system_top.v index ccf1d7b31..dab053684 100644 --- a/projects/dac_fmc_ebz/zc706/system_top.v +++ b/projects/dac_fmc_ebz/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/dac_fmc_ebz/zcu102/system_top.v b/projects/dac_fmc_ebz/zcu102/system_top.v index b79201741..f978d8d1c 100644 --- a/projects/dac_fmc_ebz/zcu102/system_top.v +++ b/projects/dac_fmc_ebz/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq2/a10soc/system_top.v b/projects/daq2/a10soc/system_top.v index 0e38e1ec6..be0e4253f 100644 --- a/projects/daq2/a10soc/system_top.v +++ b/projects/daq2/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq2/common/daq2_spi.v b/projects/daq2/common/daq2_spi.v index f07ec9d18..cfa224e58 100644 --- a/projects/daq2/common/daq2_spi.v +++ b/projects/daq2/common/daq2_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq2/kc705/system_top.v b/projects/daq2/kc705/system_top.v index 5ef2381d4..05b122064 100644 --- a/projects/daq2/kc705/system_top.v +++ b/projects/daq2/kc705/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v index e5a367be2..1901fe659 100644 --- a/projects/daq2/kcu105/system_top.v +++ b/projects/daq2/kcu105/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v index 790f629f4..867d51412 100644 --- a/projects/daq2/zc706/system_top.v +++ b/projects/daq2/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq2/zcu102/system_top.v b/projects/daq2/zcu102/system_top.v index 7815a7f83..e8562d640 100644 --- a/projects/daq2/zcu102/system_top.v +++ b/projects/daq2/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq3/common/daq3_spi.v b/projects/daq3/common/daq3_spi.v index d6a24b8b5..f9b61feaf 100644 --- a/projects/daq3/common/daq3_spi.v +++ b/projects/daq3/common/daq3_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq3/kcu105/system_top.v b/projects/daq3/kcu105/system_top.v index 00dc4a184..86c6cc765 100644 --- a/projects/daq3/kcu105/system_top.v +++ b/projects/daq3/kcu105/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq3/vcu118/system_top.v b/projects/daq3/vcu118/system_top.v index 0ebc6df8f..b0a5b5edb 100644 --- a/projects/daq3/vcu118/system_top.v +++ b/projects/daq3/vcu118/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index df609af8b..aaddea139 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/daq3/zcu102/system_top.v b/projects/daq3/zcu102/system_top.v index c8939e5f6..7af16a6a3 100644 --- a/projects/daq3/zcu102/system_top.v +++ b/projects/daq3/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcadc2/common/fmcadc2_spi.v b/projects/fmcadc2/common/fmcadc2_spi.v index 755800a68..d9a7de8bb 100644 --- a/projects/fmcadc2/common/fmcadc2_spi.v +++ b/projects/fmcadc2/common/fmcadc2_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v index 5ae40bb15..976b92115 100644 --- a/projects/fmcadc2/vc707/system_top.v +++ b/projects/fmcadc2/vc707/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v index bbbc4f7a5..f2dc2b379 100644 --- a/projects/fmcadc2/zc706/system_top.v +++ b/projects/fmcadc2/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcadc5/common/fmcadc5_spi.v b/projects/fmcadc5/common/fmcadc5_spi.v index 7f17a508b..7f631c6a7 100644 --- a/projects/fmcadc5/common/fmcadc5_spi.v +++ b/projects/fmcadc5/common/fmcadc5_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcadc5/vc707/system_top.v b/projects/fmcadc5/vc707/system_top.v index 76379ce86..50d10dd7d 100644 --- a/projects/fmcadc5/vc707/system_top.v +++ b/projects/fmcadc5/vc707/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v b/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v index 5748ee7a8..6ce53a96e 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcjesdadc1/kc705/system_top.v b/projects/fmcjesdadc1/kc705/system_top.v index c3427399d..926f292a3 100644 --- a/projects/fmcjesdadc1/kc705/system_top.v +++ b/projects/fmcjesdadc1/kc705/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcjesdadc1/vc707/system_top.v b/projects/fmcjesdadc1/vc707/system_top.v index 0136b522e..a3ce363d0 100644 --- a/projects/fmcjesdadc1/vc707/system_top.v +++ b/projects/fmcjesdadc1/vc707/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcjesdadc1/zc706/system_top.v b/projects/fmcjesdadc1/zc706/system_top.v index 3f3048881..fddeea507 100644 --- a/projects/fmcjesdadc1/zc706/system_top.v +++ b/projects/fmcjesdadc1/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms11/common/fmcomms11_spi.v b/projects/fmcomms11/common/fmcomms11_spi.v index bbf2a7f0d..9caade5fb 100644 --- a/projects/fmcomms11/common/fmcomms11_spi.v +++ b/projects/fmcomms11/common/fmcomms11_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms11/zc706/system_top.v b/projects/fmcomms11/zc706/system_top.v index 5ac0d7af0..aecb7873b 100644 --- a/projects/fmcomms11/zc706/system_top.v +++ b/projects/fmcomms11/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms2/kc705/system_top.v b/projects/fmcomms2/kc705/system_top.v index 4313af1fe..7b92301af 100644 --- a/projects/fmcomms2/kc705/system_top.v +++ b/projects/fmcomms2/kc705/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms2/kcu105/system_top.v b/projects/fmcomms2/kcu105/system_top.v index b16ea63f5..4f8e80e09 100644 --- a/projects/fmcomms2/kcu105/system_top.v +++ b/projects/fmcomms2/kcu105/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms2/vc707/system_top.v b/projects/fmcomms2/vc707/system_top.v index 943f1c982..62d98dc62 100644 --- a/projects/fmcomms2/vc707/system_top.v +++ b/projects/fmcomms2/vc707/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms2/zc702/system_top.v b/projects/fmcomms2/zc702/system_top.v index e0649e95c..9c369fe44 100644 --- a/projects/fmcomms2/zc702/system_top.v +++ b/projects/fmcomms2/zc702/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index 5e9726857..0575df070 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms2/zcu102/system_top.v b/projects/fmcomms2/zcu102/system_top.v index 59177162e..22a012cd1 100644 --- a/projects/fmcomms2/zcu102/system_top.v +++ b/projects/fmcomms2/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index cdcf01eac..1a1c44eb1 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms5/zc702/system_top.v b/projects/fmcomms5/zc702/system_top.v index 935400d65..b19407f2d 100644 --- a/projects/fmcomms5/zc702/system_top.v +++ b/projects/fmcomms5/zc702/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms5/zc706/system_top.v b/projects/fmcomms5/zc706/system_top.v index 43df46f0c..4a5acbe85 100644 --- a/projects/fmcomms5/zc706/system_top.v +++ b/projects/fmcomms5/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms5/zcu102/system_top.v b/projects/fmcomms5/zcu102/system_top.v index 22d2e3035..61e1d86bc 100644 --- a/projects/fmcomms5/zcu102/system_top.v +++ b/projects/fmcomms5/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms8/a10soc/system_top.v b/projects/fmcomms8/a10soc/system_top.v index 312940295..657280419 100755 --- a/projects/fmcomms8/a10soc/system_top.v +++ b/projects/fmcomms8/a10soc/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms8/common/fmcomms8_spi.v b/projects/fmcomms8/common/fmcomms8_spi.v index f7cda13e7..29527b22f 100644 --- a/projects/fmcomms8/common/fmcomms8_spi.v +++ b/projects/fmcomms8/common/fmcomms8_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/fmcomms8/zcu102/system_top.v b/projects/fmcomms8/zcu102/system_top.v index c1369fd91..b0a04af02 100644 --- a/projects/fmcomms8/zcu102/system_top.v +++ b/projects/fmcomms8/zcu102/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/imageon/zed/system_top.v b/projects/imageon/zed/system_top.v index 82e6a5136..8077d0161 100644 --- a/projects/imageon/zed/system_top.v +++ b/projects/imageon/zed/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/jupiter_sdr/system_top.v b/projects/jupiter_sdr/system_top.v index cd6583f57..bea7018d4 100644 --- a/projects/jupiter_sdr/system_top.v +++ b/projects/jupiter_sdr/system_top.v @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/m2k/common/m2k_spi.v b/projects/m2k/common/m2k_spi.v index 66f6e73d8..70fc4daa1 100644 --- a/projects/m2k/common/m2k_spi.v +++ b/projects/m2k/common/m2k_spi.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/m2k/standalone/system_top.v b/projects/m2k/standalone/system_top.v index 27898e9fb..b53295927 100644 --- a/projects/m2k/standalone/system_top.v +++ b/projects/m2k/standalone/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/pluto/system_top.v b/projects/pluto/system_top.v index 0a6053098..2478cb19e 100644 --- a/projects/pluto/system_top.v +++ b/projects/pluto/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_top.v b/projects/pulsar_adc_pmdz/coraz7s/system_top.v index e041b34ad..2c11755b9 100644 --- a/projects/pulsar_adc_pmdz/coraz7s/system_top.v +++ b/projects/pulsar_adc_pmdz/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2018 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR diff --git a/projects/sidekiqz2/system_top.v b/projects/sidekiqz2/system_top.v index 256c8a855..651356d46 100755 --- a/projects/sidekiqz2/system_top.v +++ b/projects/sidekiqz2/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/projects/usrpe31x/system_top.v b/projects/usrpe31x/system_top.v index db52ccf24..2cd15fb6e 100644 --- a/projects/usrpe31x/system_top.v +++ b/projects/usrpe31x/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are