Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>main
parent
2f35ce8a51
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28c06d505f
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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||||||
|
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -8,7 +8,7 @@
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// terms.
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// terms.
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//
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//
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// The user should read each of these license terms, and understand the
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// The user should read each of these license terms, and understand the
|
||||||
// freedoms and responsabilities that he or she has by using this source/core.
|
// freedoms and responsibilities that he or she has by using this source/core.
|
||||||
//
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//
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||||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||||
|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
|
// ***************************************************************************
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||||||
// ***************************************************************************
|
// ***************************************************************************
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||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
|
// ***************************************************************************
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||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -8,7 +8,7 @@
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||||||
// terms.
|
// terms.
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||||||
//
|
//
|
||||||
// The user should read each of these license terms, and understand the
|
// The user should read each of these license terms, and understand the
|
||||||
// freedoms and responsabilities that he or she has by using this source/core.
|
// freedoms and responsibilities that he or she has by using this source/core.
|
||||||
//
|
//
|
||||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||||
|
|
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@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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||||||
|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
|
// ***************************************************************************
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||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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||||||
|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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||||||
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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||||||
|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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||||||
|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
|
// ***************************************************************************
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||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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||||||
//
|
//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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|
|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
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//
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||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
|
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// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
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|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
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||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
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// In this HDL repository, there are many different and unique modules, consisting
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||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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// of various HDL (Verilog or VHDL) components. The individual modules are
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|
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@ -1,6 +1,6 @@
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||||||
// ***************************************************************************
|
// ***************************************************************************
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||||||
// ***************************************************************************
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// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
|
@ -1,6 +1,6 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
|
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||||
//
|
//
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue