projects/fmcomms2/c5soc: Add GPIO support.

projects/fmcomms2/c5soc/system_bd.qsys

@@ -81,6 +81,22 @@
          type = "String";
       }
    }
+   element gpio
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element gpio.s1
+   {
+      datum baseAddress
+      {
+         value = "65680";
+         type = "String";
+      }
+   }
    element sys_int_mem.s1
    {
       datum baseAddress
@@ -102,6 +118,14 @@
          type = "String";
       }
    }
+   element axi_dmac_dac.s_axi
+   {
+      datum baseAddress
+      {
+         value = "16384";
+         type = "String";
+      }
+   }
    element axi_ad9361.s_axi
    {
       datum baseAddress
@@ -118,14 +142,6 @@
          type = "String";
       }
    }
-   element axi_dmac_dac.s_axi
-   {
-      datum baseAddress
-      {
-         value = "16384";
-         type = "String";
-      }
-   }
    element spi_ad9361
    {
       datum _sortIndex
@@ -367,6 +383,11 @@
    internal="util_dac_unpack.channels_data"
    type="conduit"
    dir="end" />
+ <interface
+   name="gpio_external_connection"
+   internal="gpio.external_connection"
+   type="conduit"
+   dir="end" />
  <module kind="clock_source" version="14.0" enabled="1" name="sys_clk">
   <parameter name="clockFrequency" value="50000000" />
   <parameter name="clockFrequencyKnown" value="true" />
@@ -1281,6 +1302,20 @@
   <parameter name="DATA_WIDTH" value="16" />
   <parameter name="AUTO_DATA_CLOCK_CLOCK_RATE" value="0" />
  </module>
+ <module kind="altera_avalon_pio" version="14.0" enabled="1" name="gpio">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="5" />
+  <parameter name="clockRate" value="50000000" />
+ </module>
  <connection
    kind="avalon"
    version="14.0"
@@ -1574,6 +1609,21 @@
    version="14.0"
    start="sys_hps.h2f_user0_clock"
    end="sys_hps.f2h_sdram1_clock" />
+ <connection kind="clock" version="14.0" start="sys_clk.clk" end="gpio.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="gpio.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="gpio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010090" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
  <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
  <interconnectRequirement

projects/fmcomms2/c5soc/system_project.tcl

@@ -67,12 +67,20 @@ set_location_assignment PIN_E4  -to tx_data_out[5]
 set_location_assignment PIN_D4  -to "tx_data_out[5](n)"
 
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_resetb
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_en_agc
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_sync
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_enable
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_txnrx
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_mosi
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_miso
 
 set_location_assignment PIN_C4  -to ad9361_resetb
+set_location_assignment PIN_C5  -to ad9361_en_agc
+set_location_assignment PIN_D5  -to ad9361_sync
+set_location_assignment PIN_B11 -to ad9361_enable
+set_location_assignment PIN_C12 -to ad9361_txnrx
 set_location_assignment PIN_A8  -to spi_csn
 set_location_assignment PIN_H12 -to spi_clk
 set_location_assignment PIN_H13 -to spi_mosi

projects/fmcomms2/c5soc/system_top.v

@@ -134,7 +134,11 @@ module system_top (
 
   // gpio interface
 
-  ad9361_resetb,
+  ad9361_resetb,
+  ad9361_en_agc,
+  ad9361_sync,
+  ad9361_enable,
+  ad9361_txnrx,
 
   // spi
 
@@ -238,7 +242,11 @@ module system_top (
 
   // gpio interface
 
-  output            ad9361_resetb;
+  output            ad9361_resetb;
+  output            ad9361_en_agc;
+  output            ad9361_sync;
+  output            ad9361_enable;
+  output            ad9361_txnrx;
 
   // spi interface
 
@@ -303,8 +311,6 @@ module system_top (
   assign vga_vs = vid_v_sync;
   assign {vga_b,vga_g,vga_r} =  {vid_b,vid_g,vid_r};
 
-  assign ad9361_resetb = 1'b1;
-
   // instantiations
 
   sld_signaltap #(
@@ -506,7 +512,8 @@ module system_top (
 		.util_dac_unpack_channels_data_dac_data_03 (dac_data_q1),
 		.util_dac_unpack_channels_data_fifo_valid (dac_fifo_valid),
 		.util_dac_unpack_channels_data_dma_rd (dac_rd_en),
-		.util_dac_unpack_channels_data_dma_data (dac_ddata)
+		.util_dac_unpack_channels_data_dma_data (dac_ddata),
+		.gpio_external_connection_export ({ad9361_resetb, ad9361_en_agc, ad9361_sync, ad9361_enable, ad9361_txnrx})
 	);
 
 endmodule