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axi-jesd-xcvr- parameter changes

main
Rejeesh Kutty 2015-08-19 14:55:08 -04:00
parent 928ee4972b
commit 28eb09b4d5
1 changed files with 19 additions and 19 deletions
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38
library/axi_jesd_xcvr/axi_jesd_xcvr.v
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@ -99,8 +99,8 @@ module axi_jesd_xcvr (
parameter ID = 0; parameter ID = 0;
parameter DEVICE_TYPE = 0; parameter DEVICE_TYPE = 0;
parameter PCORE_NUM_OF_TX_LANES = 4; parameter TX_NUM_OF_LANES = 4;
parameter PCORE_NUM_OF_RX_LANES = 4; parameter RX_NUM_OF_LANES = 4;
output rst; output rst;
@ -111,14 +111,14 @@ module axi_jesd_xcvr (
input rx_ext_sysref_in; input rx_ext_sysref_in;
output rx_ext_sysref_out; output rx_ext_sysref_out;
output rx_sync; output rx_sync;
output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_sof; output [((RX_NUM_OF_LANES* 1)-1):0] rx_sof;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_data; output [((RX_NUM_OF_LANES*32)-1):0] rx_data;
input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_ready; input [((RX_NUM_OF_LANES* 1)-1):0] rx_ready;
output rx_ip_sysref; output rx_ip_sysref;
input rx_ip_sync; input rx_ip_sync;
input [ 3:0] rx_ip_sof; input [ 3:0] rx_ip_sof;
input rx_ip_valid; input rx_ip_valid;
input [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data; input [((RX_NUM_OF_LANES*32)-1):0] rx_ip_data;
output rx_ip_ready; output rx_ip_ready;
// transmit interface // transmit interface
@ -128,12 +128,12 @@ module axi_jesd_xcvr (
input tx_ext_sysref_in; input tx_ext_sysref_in;
output tx_ext_sysref_out; output tx_ext_sysref_out;
input tx_sync; input tx_sync;
input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_data; input [((TX_NUM_OF_LANES*32)-1):0] tx_data;
input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] tx_ready; input [((RX_NUM_OF_LANES* 1)-1):0] tx_ready;
output tx_ip_sysref; output tx_ip_sysref;
output tx_ip_sync; output tx_ip_sync;
output tx_ip_valid; output tx_ip_valid;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] tx_ip_data; output [((RX_NUM_OF_LANES*32)-1):0] tx_ip_data;
input tx_ip_ready; input tx_ip_ready;
// axi interface // axi interface
@ -166,7 +166,7 @@ module axi_jesd_xcvr (
wire up_clk; wire up_clk;
wire [ 7:0] status_s; wire [ 7:0] status_s;
wire [ 3:0] rx_ip_sof_s; wire [ 3:0] rx_ip_sof_s;
wire [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data_s; wire [((RX_NUM_OF_LANES*32)-1):0] rx_ip_data_s;
wire [ 7:0] rx_status_s; wire [ 7:0] rx_status_s;
wire [ 7:0] tx_status_s; wire [ 7:0] tx_status_s;
wire up_wreq_s; wire up_wreq_s;
@ -197,7 +197,7 @@ module axi_jesd_xcvr (
assign rx_ip_sof_s[0] = rx_ip_sof[3]; assign rx_ip_sof_s[0] = rx_ip_sof[3];
generate generate
for (n = 0; n < PCORE_NUM_OF_RX_LANES; n = n + 1) begin: g_rx_swap for (n = 0; n < RX_NUM_OF_LANES; n = n + 1) begin: g_rx_swap
assign rx_ip_data_s[((n*32) + 31):((n*32) + 24)] = rx_ip_data[((n*32) + 7):((n*32) + 0)]; assign rx_ip_data_s[((n*32) + 31):((n*32) + 24)] = rx_ip_data[((n*32) + 7):((n*32) + 0)];
assign rx_ip_data_s[((n*32) + 23):((n*32) + 16)] = rx_ip_data[((n*32) + 15):((n*32) + 8)]; assign rx_ip_data_s[((n*32) + 23):((n*32) + 16)] = rx_ip_data[((n*32) + 15):((n*32) + 8)];
assign rx_ip_data_s[((n*32) + 15):((n*32) + 8)] = rx_ip_data[((n*32) + 23):((n*32) + 16)]; assign rx_ip_data_s[((n*32) + 15):((n*32) + 8)] = rx_ip_data[((n*32) + 23):((n*32) + 16)];
@ -206,16 +206,16 @@ module axi_jesd_xcvr (
endgenerate endgenerate
generate generate
if (PCORE_NUM_OF_RX_LANES < 8) begin if (RX_NUM_OF_LANES < 8) begin
assign rx_status_s[7:PCORE_NUM_OF_RX_LANES] = status_s[7:PCORE_NUM_OF_RX_LANES]; assign rx_status_s[7:RX_NUM_OF_LANES] = status_s[7:RX_NUM_OF_LANES];
assign rx_status_s[(PCORE_NUM_OF_RX_LANES-1):0] = rx_ready; assign rx_status_s[(RX_NUM_OF_LANES-1):0] = rx_ready;
end else begin end else begin
assign rx_status_s = rx_ready[7:0]; assign rx_status_s = rx_ready[7:0];
end end
endgenerate endgenerate
generate generate
for (n = 0; n < PCORE_NUM_OF_RX_LANES; n = n + 1) begin: g_rx_align for (n = 0; n < RX_NUM_OF_LANES; n = n + 1) begin: g_rx_align
ad_jesd_align i_jesd_align ( ad_jesd_align i_jesd_align (
.rx_clk (rx_clk), .rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof_s), .rx_ip_sof (rx_ip_sof_s),
@ -229,7 +229,7 @@ module axi_jesd_xcvr (
assign tx_ip_sysref = tx_ext_sysref_out; assign tx_ip_sysref = tx_ext_sysref_out;
generate generate
for (n = 0; n < PCORE_NUM_OF_TX_LANES; n = n + 1) begin: g_tx_swap for (n = 0; n < TX_NUM_OF_LANES; n = n + 1) begin: g_tx_swap
assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)]; assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)];
assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)]; assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)];
assign tx_ip_data[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)]; assign tx_ip_data[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)];
@ -238,9 +238,9 @@ module axi_jesd_xcvr (
endgenerate endgenerate
generate generate
if (PCORE_NUM_OF_TX_LANES < 8) begin if (TX_NUM_OF_LANES < 8) begin
assign tx_status_s[7:PCORE_NUM_OF_TX_LANES] = status_s[7:PCORE_NUM_OF_TX_LANES]; assign tx_status_s[7:TX_NUM_OF_LANES] = status_s[7:TX_NUM_OF_LANES];
assign tx_status_s[(PCORE_NUM_OF_TX_LANES-1):0] = tx_ready; assign tx_status_s[(TX_NUM_OF_LANES-1):0] = tx_ready;
end else begin end else begin
assign tx_status_s = tx_ready[7:0]; assign tx_status_s = tx_ready[7:0];
end end