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axi_logic_analyzer: Fixed triggered flag

main
Adrian Costina 2017-07-03 12:59:24 +03:00
parent b0ebf2df06
commit 291718d6a8
3 changed files with 34 additions and 9 deletions
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28
library/axi_logic_analyzer/axi_logic_analyzer.v
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@ -97,6 +97,15 @@ module axi_logic_analyzer (
reg [31:0] delay_counter = 'd0;
reg triggered = 'd0;
reg up_triggered;
reg up_triggered_d1;
reg up_triggered_d2;
reg up_triggered_set;
reg up_triggered_reset;
reg up_triggered_reset_d1;
reg up_triggered_reset_d2;
// internal signals
wire up_clk;
@ -142,6 +151,23 @@ module axi_logic_analyzer (
assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s : trigger_out_delayed;
assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
always @(posedge clk_out) begin
if (sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
up_triggered_set <= 1'b1;
end else if (up_triggered_reset == 1'b1) begin
up_triggered_set <= 1'b0;
end
up_triggered_reset_d1 <= up_triggered;
up_triggered_reset_d2 <= up_triggered_reset_d1;
up_triggered_reset <= up_triggered_reset_d2;
end
always @(posedge up_clk) begin
up_triggered_d1 <= up_triggered_set;
up_triggered_d2 <= up_triggered_d1;
up_triggered <= up_triggered_d2;
end
generate
for (i = 0 ; i < 16; i = i + 1) begin
assign data_t[i] = od_pp_n[i] ? io_selection[i] & !data_o[i] : io_selection[i];
@ -282,7 +308,7 @@ module axi_logic_analyzer (
.input_data (adc_data),
.od_pp_n (od_pp_n),
.triggered (trigger_out),
.triggered (up_triggered),
// bus interface

2
library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
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@ -29,3 +29,5 @@ set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS
set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]

13
library/axi_logic_analyzer/axi_logic_analyzer_reg.v
View File

@ -96,7 +96,6 @@ module axi_logic_analyzer_reg (
reg up_triggered = 0;
wire [15:0] up_input_data;
wire adc_triggered;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
@ -168,10 +167,10 @@ module axi_logic_analyzer_reg (
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_trigger_delay <= up_wdata;
end
if (adc_triggered == 1'b1) begin
if (triggered == 1'b1) begin
up_triggered <= 1'b1;
end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_triggered <= up_wdata[0];
up_triggered <= up_triggered & ~up_wdata[0];
end
end
end
@ -253,21 +252,19 @@ module axi_logic_analyzer_reg (
divider_counter_pg, // 32
divider_counter_la})); // 32
up_xfer_status #(.DATA_WIDTH(17)) i_xfer_status (
up_xfer_status #(.DATA_WIDTH(16)) i_xfer_status (
// up interface
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_status({ up_input_data,
adc_triggered}),
.up_data_status(up_input_data),
// device interface
.d_rst(1'd0),
.d_clk(clk),
.d_data_status({ input_data,
triggered}));
.d_data_status(input_data));
endmodule