fmcomms2: c5soc project updated to 14.1
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14e23b106c
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293ec6a319
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@ -6,7 +6,7 @@ create_clock -period "12.500 ns" -name clk_80m [get_pins {i_system_bd|sys_hps|f
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derive_pll_clocks
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derive_clock_uncertainty
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set clk_125m [get_clocks {i_system_bd|axi_ad9361|i_ad9361|i_dev_if|i_rx|i_altlvds_rx|auto_generated|pll_sclk~PLL_OUTPUT_COUNTER|divclk}]
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set clk_125m [get_clocks {i_system_bd|axi_ad9361|i_dev_if|i_rx|i_altlvds_rx|auto_generated|pll_sclk~PLL_OUTPUT_COUNTER|divclk}]
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set clk_vga [get_clocks {i_system_bd|vga_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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