zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad9081: Proper reset sequence for versal transceivers 

- Removes the reset_tx_pll_and_datapath_in reset
- Connects gtreset_in to make use of the master reset found inside
the Transceiver Bridge IP
- Connects the necessary signals for the master reset between the
Transceiver Wizard and Transceiver Bridge

ad9209/vck190/system_top: Connect versal transceiver reset

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
main
Bogdan Luncan 2023-05-10 11:06:44 +01:00 committed by Bogdan Luncan
parent e530b3feec
commit 294b681196
5 changed files with 77 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
View File

@ -175,7 +175,9 @@ if {$ADI_PHY_SEL == 1} {
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \
? $ad_project_params(REF_CLK_RATE) : 360 } ]
? $ad_project_params(REF_CLK_RATE) : 375 } ]
create_bd_port -dir I gt_reset
switch $INTF_CFG {
"RXTX" {
@ -188,7 +190,7 @@ if {$ADI_PHY_SEL == 1} {
"TX" {
create_versal_phy jesd204_phy $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG
}
}
}
}
# Instantiate ADC (Rx) path
@ -346,13 +348,13 @@ if {$ADI_PHY_SEL == 1} {
}
} else {
ad_connect ref_clk_q0 jesd204_phy/GT_REFCLK
ad_connect gt_reset jesd204_phy/gtreset_in
if {$INTF_CFG != "TX"} {
set rx_link_clock jesd204_phy/rxusrclk_out
# Connect PHY to Link Layer
for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} {
ad_connect axi_mxfe_rx_jesd/rx_phy${j} jesd204_phy/rx${j}
}
ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy/reset_rx_pll_and_datapath_in
ad_connect $rx_link_clock /axi_mxfe_rx_jesd/link_clk
ad_connect rx_device_clk /axi_mxfe_rx_jesd/device_clk
@ -367,7 +369,6 @@ if {$ADI_PHY_SEL == 1} {
for {set j 0} {$j < $TX_NUM_OF_LANES} {incr j} {
ad_connect axi_mxfe_tx_jesd/tx_phy${j} jesd204_phy/tx${j}
}
ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy/reset_tx_pll_and_datapath_in
ad_connect $tx_link_clock /axi_mxfe_tx_jesd/link_clk
ad_connect tx_device_clk /axi_mxfe_tx_jesd/device_clk

81
projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
View File

@ -1,9 +1,9 @@
proc create_versal_phy {
{ip_name versal_phy}
{num_lanes 2}
{rx_lane_rate 11.88}
{tx_lane_rate 11.88}
{ref_clock 360}
{num_lanes 4}
{rx_lane_rate 24.75}
{tx_lane_rate 24.75}
{ref_clock 375}
{intf_cfg RXTX}
} {
@ -27,14 +27,13 @@ create_bd_cell -type hier ${ip_name}
# Common interface
if {$intf_cfg != "TX"} {
create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
create_bd_pin -dir I ${ip_name}/reset_rx_pll_and_datapath_in
}
if {$intf_cfg != "RX"} {
create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk
create_bd_pin -dir I ${ip_name}/reset_tx_pll_and_datapath_in
}
create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk
create_bd_pin -dir I ${ip_name}/apb3clk -type clk
create_bd_pin -dir I ${ip_name}/gtreset_in
ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0
set_property -dict [list \
@ -211,7 +210,7 @@ for {set j 0} {$j < $num_quads} {incr j} {
ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx_${j}
ad_connect ${ip_name}/gt_quad_base_${j}/ch0_txoutclk ${ip_name}/bufg_gt_tx_${j}/outclk
}
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 ${ip_name}/GT_Serial_${j}
ad_connect ${ip_name}/gt_quad_base_${j}/GT_Serial ${ip_name}/GT_Serial_${j}
}
@ -233,9 +232,6 @@ if {$intf_cfg != "TX"} {
ad_connect ${ip_name}/bufg_gt_rx_${quad_index}/usrclk ${ip_name}/rx_adapt_${j}/usr_clk
}
# Clocks and resets
ad_connect ${ip_name}/reset_rx_pll_and_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_pll_and_datapath_in
}
if {$intf_cfg != "RX"} {
ad_connect ${ip_name}/bufg_gt_tx_0/usrclk ${ip_name}/gt_bridge_ip_0/gt_txusrclk
@ -254,8 +250,6 @@ if {$intf_cfg != "RX"} {
ad_connect ${ip_name}/bufg_gt_tx_${quad_index}/usrclk ${ip_name}/tx_adapt_${j}/usr_clk
}
# Clocks and resets
ad_connect ${ip_name}/reset_tx_pll_and_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_pll_and_datapath_in
}
for {set i 0} {$i < $num_quads} {incr i} {
@ -269,9 +263,8 @@ for {set i 0} {$i < $num_quads} {incr i} {
}
}
# Clocks and resets
# Clocks and gtpowergood
ad_connect ${ip_name}/apb3clk ${ip_name}/gt_bridge_ip_0/apb3clk
ad_connect GND ${ip_name}/gt_bridge_ip_0/gtreset_in
ad_ip_instance xlconcat ${ip_name}/xlconcat_0 [list \
NUM_PORTS $num_quads \
@ -289,4 +282,64 @@ for {set j 0} {$j < $num_quads} {incr j} {
ad_connect ${ip_name}/xlconcat_0/dout ${ip_name}/util_reduced_logic_0/Op1
ad_connect ${ip_name}/util_reduced_logic_0/Res ${ip_name}/gt_bridge_ip_0/gtpowergood
# Reset
ad_connect ${ip_name}/gtreset_in ${ip_name}/gt_bridge_ip_0/gtreset_in
for {set j 0} {$j < ${num_lanes}} {incr j} {
set quad_index [expr int($j / 4)]
set ch_index [expr $j % 4]
ad_connect ${ip_name}/gt_bridge_ip_0/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset
}
ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone [list \
NUM_PORTS ${num_lanes} \
]
ad_ip_instance util_reduced_logic ${ip_name}/util_reduced_logic_iloresetdone [list \
C_SIZE ${num_lanes} \
]
for {set j 0} {$j < ${num_lanes}} {incr j} {
set quad_index [expr int($j / 4)]
set ch_index [expr $j % 4]
ad_connect ${ip_name}/xlconcat_iloresetdone/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone
}
ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/util_reduced_logic_iloresetdone/Op1
ad_connect ${ip_name}/util_reduced_logic_iloresetdone/Res ${ip_name}/gt_bridge_ip_0/ilo_resetdone
for {set j 0} {$j < ${num_quads}} {incr j} {
ad_connect ${ip_name}/gt_bridge_ip_0/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk0_lcpllreset
ad_connect ${ip_name}/gt_bridge_ip_0/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk1_lcpllreset
}
set num_cplllocks [expr 2 * ${num_quads}]
ad_ip_instance xlconcat ${ip_name}/xlconcat_cplllock [list \
NUM_PORTS ${num_cplllocks} \
]
ad_ip_instance util_reduced_logic ${ip_name}/util_reduced_logic_cplllock [list \
C_SIZE ${num_cplllocks} \
]
for {set j 0} {$j < ${num_quads}} {incr j} {
set in_index_0 [expr $j * 2 + 0]
set in_index_1 [expr $j * 2 + 1]
ad_connect ${ip_name}/xlconcat_cplllock/In${in_index_0} ${ip_name}/gt_quad_base_${j}/hsclk0_lcplllock
ad_connect ${ip_name}/xlconcat_cplllock/In${in_index_1} ${ip_name}/gt_quad_base_${j}/hsclk1_lcplllock
}
ad_connect ${ip_name}/xlconcat_cplllock/dout ${ip_name}/util_reduced_logic_cplllock/Op1
ad_connect ${ip_name}/util_reduced_logic_cplllock/Res ${ip_name}/gt_bridge_ip_0/gt_lcpll_lock
ad_ip_instance xlconcat ${ip_name}/xlconcat_ch [list \
NUM_PORTS ${num_lanes} \
]
for {set j 0} {$j < ${num_lanes}} {incr j} {
set quad_index [expr int($j / 4)]
set ch_index [expr $j % 4]
ad_ip_instance xlslice ${ip_name}/slice_ch${j} [list \
DIN_WIDTH 16 \
]
ad_connect ${ip_name}/slice_ch${j}/Din ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_pcsrsvdout
ad_connect ${ip_name}/slice_ch${j}/Dout ${ip_name}/xlconcat_ch/In${j}
}
ad_connect ${ip_name}/xlconcat_ch/dout ${ip_name}/gt_bridge_ip_0/ch_phystatus_in
}

1
projects/ad9081_fmca_ebz/vck190/system_top.v
View File

@ -299,6 +299,7 @@ module system_top #(
.GT_Serial_1_0_grx_p (rx_data_p_loc[7:4]),
.GT_Serial_1_0_grx_n (rx_data_n_loc[7:4]),
.gt_reset (~rstb),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),

6
projects/ad9081_fmca_ebz/vck190/timing_constr.xdc
View File

@ -1,9 +1,9 @@
# Primary clock definitions
create_clock -name refclk -period 2.66 [get_ports fpga_refclk_in_p]
create_clock -name refclk -period 2.667 [get_ports fpga_refclk_in_p]
# device clock
create_clock -name tx_device_clk -period 4 [get_ports clkin6_p]
create_clock -name rx_device_clk -period 4 [get_ports clkin10_p]
create_clock -name tx_device_clk -period 4.000 [get_ports clkin6_p]
create_clock -name rx_device_clk -period 4.000 [get_ports clkin10_p]
# Constraint SYSREFs
# Assumption is that REFCLK and SYSREF have similar propagation delay,

1
projects/ad9209_fmca_ebz/vck190/system_top.v
View File

@ -250,6 +250,7 @@ module system_top #(
.GT_Serial_1_0_grx_p (rx_data_p_loc[7:4]),
.GT_Serial_1_0_grx_n (rx_data_n_loc[7:4]),
.gt_reset (~rstb),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),