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library- drp moved to up-clock domain

main
Rejeesh Kutty 2015-06-01 14:52:52 -04:00
parent f9ffaf457d
commit 297e885981
19 changed files with 181 additions and 227 deletions
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16
library/axi_ad6676/axi_ad6676.v
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@ -267,15 +267,13 @@ module axi_ad6676 (
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),

16
library/axi_ad9152/axi_ad9152_core.v
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@ -220,15 +220,13 @@ module axi_ad9152_core (
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd40),
.drp_clk (up_clk),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (32'd0),

16
library/axi_ad9234/axi_ad9234.v
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@ -267,15 +267,13 @@ module axi_ad9234 (
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),

16
library/axi_ad9250/axi_ad9250.v
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@ -267,15 +267,13 @@ module axi_ad9250 (
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),

16
library/axi_ad9361/axi_ad9361_rx.v
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@ -353,15 +353,13 @@ module axi_ad9361_rx (
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd3),
.up_adc_gpio_in (up_adc_gpio_in),

16
library/axi_ad9361/axi_ad9361_tx.v
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@ -365,15 +365,13 @@ module axi_ad9361_tx (
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd1),
.drp_clk (1'b0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (up_dac_gpio_in),

50
library/axi_ad9434/axi_ad9434.v
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@ -135,7 +135,6 @@ module axi_ad9434 (
wire mmcm_rst;
wire up_clk;
wire adc_clk;
wire drp_clk;
// internal signals
wire up_wreq_s;
@ -160,14 +159,13 @@ module axi_ad9434 (
wire delay_locked_s;
wire drp_sel_s;
wire drp_rst_s;
wire drp_wr_s;
wire [11:0] drp_addr_s;
wire [15:0] drp_wdata_s;
wire [15:0] drp_rdata_s;
wire drp_ready_s;
wire drp_locked_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire [47:0] adc_data_if_s;
wire adc_or_if_s;
@ -175,7 +173,6 @@ module axi_ad9434 (
// clock/reset assignments
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign drp_clk = up_clk;
// single channel always enable
assign adc_enable = 1'b1;
@ -203,15 +200,14 @@ module axi_ad9434 (
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.mmcm_rst(mmcm_rst),
.drp_clk(drp_clk),
.drp_rst(drp_rst_s),
.drp_sel(drp_sel_s),
.drp_wr(drp_wr_s),
.drp_addr(drp_addr_s),
.drp_wdata(drp_wdata_s),
.drp_rdata(drp_rdata_s),
.drp_ready(drp_ready_s),
.drp_locked(drp_locked_s));
.up_rstn(up_rstn),
.up_drp_sel(up_drp_sel_s),
.up_drp_wr(up_drp_wr_s),
.up_drp_addr(up_drp_addr_s),
.up_drp_wdata(up_drp_wdata_s),
.up_drp_rdata(up_drp_rdata_s),
.up_drp_ready(up_drp_ready_s),
.up_drp_locked(up_drp_locked_s));
// common processor control
axi_ad9434_core #(.PCORE_ID(PCORE_ID))
@ -231,15 +227,13 @@ module axi_ad9434 (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.drp_clk (drp_clk),
.drp_rst (drp_rst_s),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ready (drp_ready_s),
.drp_locked (drp_locked_s),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),

48
library/axi_ad9434/axi_ad9434_core.v
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@ -56,15 +56,13 @@ module axi_ad9434_core (
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// delay interface
@ -108,15 +106,13 @@ module axi_ad9434_core (
input dma_dovf;
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// delay interface
output [12:0] up_dld;
@ -225,15 +221,13 @@ module axi_ad9434_core (
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),

54
library/axi_ad9434/axi_ad9434_if.v
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@ -72,15 +72,14 @@ module axi_ad9434_if (
mmcm_rst,
// drp interface for MMCM
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked);
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter PCORE_DEVTYPE = 0; // 0 - 7Series / 1 - 6Series
@ -122,15 +121,14 @@ module axi_ad9434_if (
input mmcm_rst;
// drp interface
input drp_clk;
input drp_rst;
input drp_sel;
input drp_wr;
input [11:0] drp_addr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
output drp_locked;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
@ -225,15 +223,15 @@ module axi_ad9434_if (
.clk_in_n (adc_clk_in_n),
.clk (adc_clk_in),
.div_clk (adc_div_clk),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked));
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
// adc overange
assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3];
@ -244,7 +242,7 @@ module axi_ad9434_if (
adc_status_m1 <= 1'b0;
adc_status <= 1'b0;
end else begin
adc_status_m1 <= drp_locked & delay_locked;
adc_status_m1 <= up_drp_locked & delay_locked;
end
end

16
library/axi_ad9467/axi_ad9467.v
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@ -275,15 +275,13 @@ module axi_ad9467(
.up_status_pn_err (up_status_pn_err_s),
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.drp_clk (1'b0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'b0),
.drp_ready (1'b0),
.drp_locked (1'b1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'b0),
.up_drp_ready (1'b0),
.up_drp_locked (1'b1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),

16
library/axi_ad9625/axi_ad9625.v
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@ -231,15 +231,13 @@ module axi_ad9625 (
.up_status_pn_err (up_adc_pn_err_s),
.up_status_pn_oos (up_adc_pn_oos_s),
.up_status_or (up_adc_or_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),

16
library/axi_ad9643/axi_ad9643.v
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@ -326,15 +326,13 @@ module axi_ad9643 (
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (up_adc_gpio_in),

16
library/axi_ad9652/axi_ad9652.v
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@ -322,15 +322,13 @@ module axi_ad9652 (
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (up_adc_gpio_in),

16
library/axi_ad9671/axi_ad9671.v
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@ -286,15 +286,13 @@ module axi_ad9671 (
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd7),
.up_adc_gpio_in (32'd0),

16
library/axi_ad9739a/axi_ad9739a_core.v
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@ -223,15 +223,13 @@ module axi_ad9739a_core (
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.drp_clk (up_clk),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd1),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd1),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd1),
.up_dac_gpio_in (32'd0),

16
library/axi_generic_adc/axi_generic_adc.v
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@ -94,15 +94,13 @@ up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),

16
library/axi_mc_controller/axi_mc_controller.v
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@ -696,15 +696,13 @@ up_adc_common i_up_adc_common(
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),
.drp_wr(),
.drp_addr(),
.drp_wdata(),
.drp_rdata(16'd0),
.drp_ready(1'b0),
.drp_locked(1'b0),
.up_drp_sel(),
.up_drp_wr(),
.up_drp_addr(),
.up_drp_wdata(),
.up_drp_rdata(16'd0),
.up_drp_ready(1'b0),
.up_drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd7),
.up_adc_gpio_in(32'h0),

16
library/axi_mc_current_monitor/axi_mc_current_monitor.v
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@ -402,15 +402,13 @@ up_adc_common i_up_adc_common(
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),
.drp_wr(),
.drp_addr(),
.drp_wdata(),
.drp_rdata(16'd0),
.drp_ready(1'b0),
.drp_locked(1'b0),
.up_drp_sel(),
.up_drp_wr(),
.up_drp_addr(),
.up_drp_wdata(),
.up_drp_rdata(16'd0),
.up_drp_ready(1'b0),
.up_drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd3),

16
library/axi_mc_speed/axi_mc_speed.v
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@ -194,15 +194,13 @@ up_adc_common i_up_adc_common(
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),
.drp_wr(),
.drp_addr(),
.drp_wdata(),
.drp_rdata(16'd0),
.drp_ready(1'b0),
.drp_locked(1'b0),
.up_drp_sel(),
.up_drp_wr(),
.up_drp_addr(),
.up_drp_wdata(),
.up_drp_rdata(16'd0),
.up_drp_ready(1'b0),
.up_drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd2),
.up_adc_gpio_in(32'h0),