ad9361- ensm through dev-if
Rejeesh Kutty
parent
d82d37c23f
commit
29b0ec0378
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@ -59,6 +59,11 @@ module axi_ad9361_dev_if (
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tx_data_out_p,
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tx_data_out_n,
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// ensm control
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enable,
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txnrx,
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// clock (common to both receive and transmit)
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rst,
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@ -79,9 +84,17 @@ module axi_ad9361_dev_if (
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dac_data,
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dac_r1_mode,
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// tdd interface
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tdd_enable,
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tdd_txnrx,
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tdd_mode,
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// delay interface
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up_clk,
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up_enable,
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up_txnrx,
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up_adc_dld,
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up_adc_dwdata,
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up_adc_drdata,
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@ -97,8 +110,6 @@ module axi_ad9361_dev_if (
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parameter DEVICE_TYPE = 0;
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parameter DAC_IODELAY_ENABLE = 0;
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parameter IO_DELAY_GROUP = "dev_if_delay_group";
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localparam PCORE_7SERIES = 0;
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localparam PCORE_VIRTEX6 = 1;
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// physical interface (receive)
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@ -118,6 +129,11 @@ module axi_ad9361_dev_if (
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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// ensm control
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output enable;
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output txnrx;
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// clock (common to both receive and transmit)
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input rst;
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@ -138,15 +154,23 @@ module axi_ad9361_dev_if (
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input [47:0] dac_data;
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input dac_r1_mode;
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// tdd interface
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input tdd_enable;
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input tdd_txnrx;
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input tdd_mode;
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// delay interface
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input up_clk;
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input up_enable;
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input up_txnrx;
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input [ 6:0] up_adc_dld;
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input [34:0] up_adc_dwdata;
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output [34:0] up_adc_drdata;
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input [ 7:0] up_dac_dld;
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input [39:0] up_dac_dwdata;
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output [39:0] up_dac_drdata;
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input [ 9:0] up_dac_dld;
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input [49:0] up_dac_dwdata;
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output [49:0] up_dac_drdata;
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input delay_clk;
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input delay_rst;
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output delay_locked;
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@ -191,6 +215,18 @@ module axi_ad9361_dev_if (
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reg tx_p_frame = 'd0;
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reg [ 5:0] tx_p_data_p = 'd0;
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reg [ 5:0] tx_p_data_n = 'd0;
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reg up_enable_int = 'd0;
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reg up_txnrx_int = 'd0;
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reg enable_up_m1 = 'd0;
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reg txnrx_up_m1 = 'd0;
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reg enable_up = 'd0;
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reg txnrx_up = 'd0;
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reg enable_int = 'd0;
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reg txnrx_int = 'd0;
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reg enable_n_int = 'd0;
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reg txnrx_n_int = 'd0;
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reg enable_p_int = 'd0;
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reg txnrx_p_int = 'd0;
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// internal signals
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@ -372,6 +408,47 @@ module axi_ad9361_dev_if (
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tx_p_data_n <= tx_n_data_n;
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end
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// tdd/ensm control
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always @(posedge up_clk) begin
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up_enable_int <= up_enable;
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up_txnrx_int <= up_txnrx;
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end
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always @(posedge clk or posedge rst) begin
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if (rst == 1'b1) begin
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enable_up_m1 <= 1'b0;
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txnrx_up_m1 <= 1'b0;
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enable_up <= 1'b0;
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txnrx_up <= 1'b0;
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end else begin
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enable_up_m1 <= up_enable_int;
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txnrx_up_m1 <= up_txnrx_int;
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enable_up <= enable_up_m1;
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txnrx_up <= txnrx_up_m1;
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end
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end
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always @(posedge clk) begin
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if (tdd_mode == 1'b1) begin
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enable_int <= tdd_enable;
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txnrx_int <= tdd_txnrx;
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end else begin
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enable_int <= enable_up;
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txnrx_int <= txnrx_up;
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end
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end
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always @(negedge clk) begin
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enable_n_int <= enable_int;
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txnrx_n_int <= txnrx_int;
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end
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always @(posedge l_clk) begin
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enable_p_int <= enable_n_int;
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txnrx_p_int <= txnrx_n_int;
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end
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// receive data interface, ibuf -> idelay -> iddr
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generate
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@ -422,6 +499,7 @@ module axi_ad9361_dev_if (
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for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
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ad_lvds_out #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.SINGLE_ENDED (0),
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.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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@ -445,6 +523,7 @@ module axi_ad9361_dev_if (
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ad_lvds_out #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.SINGLE_ENDED (0),
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.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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@ -466,6 +545,7 @@ module axi_ad9361_dev_if (
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ad_lvds_out #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.SINGLE_ENDED (0),
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.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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@ -483,6 +563,50 @@ module axi_ad9361_dev_if (
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.delay_rst (delay_rst),
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.delay_locked ());
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// enable, oddr -> obuf
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ad_lvds_out #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.SINGLE_ENDED (1),
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.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_enable (
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.tx_clk (l_clk),
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.tx_data_p (enable_p_int),
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.tx_data_n (enable_p_int),
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.tx_data_out_p (enable),
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.tx_data_out_n (),
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.up_clk (up_clk),
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.up_dld (up_dac_dld[8]),
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.up_dwdata (up_dac_dwdata[44:40]),
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.up_drdata (up_dac_drdata[44:40]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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// txnrx, oddr -> obuf
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ad_lvds_out #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.SINGLE_ENDED (1),
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.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_txnrx (
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.tx_clk (l_clk),
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.tx_data_p (txnrx_p_int),
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.tx_data_n (txnrx_p_int),
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.tx_data_out_p (txnrx),
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.tx_data_out_n (),
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.up_clk (up_clk),
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.up_dld (up_dac_dld[9]),
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.up_dwdata (up_dac_dwdata[49:45]),
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.up_drdata (up_dac_drdata[49:45]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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// device clock interface (receive clock)
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ad_lvds_clk #(
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