diff --git a/library/altera/adi_jesd204/Makefile b/library/altera/adi_jesd204/Makefile index 32de6f161..d1cc72837 100644 --- a/library/altera/adi_jesd204/Makefile +++ b/library/altera/adi_jesd204/Makefile @@ -5,6 +5,8 @@ LIBRARY_NAME := adi_jesd204 +ALTERA_DEPS += adi_jesd204_glue.v +ALTERA_DEPS += adi_jesd204_glue_hw.tcl ALTERA_DEPS += adi_jesd204_hw.tcl ALTERA_LIB_DEPS += altera/axi_adxcvr diff --git a/library/altera/adi_jesd204/adi_jesd204_glue.v b/library/altera/adi_jesd204/adi_jesd204_glue.v new file mode 100644 index 000000000..c3fe9d025 --- /dev/null +++ b/library/altera/adi_jesd204/adi_jesd204_glue.v @@ -0,0 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +module adi_jesd204_glue ( + input in_pll_powerdown, + output out_pll_powerdown, + output out_mcgb_rst +); + +assign out_pll_powerdown = in_pll_powerdown; +assign out_mcgb_rst = in_pll_powerdown; + +endmodule diff --git a/library/altera/adi_jesd204/adi_jesd204_glue_hw.tcl b/library/altera/adi_jesd204/adi_jesd204_glue_hw.tcl new file mode 100644 index 000000000..cdd8f3704 --- /dev/null +++ b/library/altera/adi_jesd204/adi_jesd204_glue_hw.tcl @@ -0,0 +1,68 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +package require qsys +source ../../scripts/adi_env.tcl +source ../../scripts/adi_ip_alt.tcl + + +ad_ip_create adi_jesd204_glue {Glue} jesd204_phy_glue_elab +set_module_property INTERNAL true + +# files + +ad_ip_files adi_jesd204_glue [list \ + adi_jesd204_glue.v \ +] + +# parameters + +proc jesd204_phy_glue_elab {} { + add_interface in_pll_powerdown conduit end + add_interface_port in_pll_powerdown in_pll_powerdown pll_powerdown Input 1 + add_interface out_pll_powerdown conduit end + add_interface_port out_pll_powerdown out_pll_powerdown pll_powerdown Output 1 + add_interface out_mcgb_rst conduit end + add_interface_port out_mcgb_rst out_mcgb_rst mcgb_rst Output 1 +} diff --git a/library/altera/adi_jesd204/adi_jesd204_hw.tcl b/library/altera/adi_jesd204/adi_jesd204_hw.tcl index 0abf34b65..2f7966570 100644 --- a/library/altera/adi_jesd204/adi_jesd204_hw.tcl +++ b/library/altera/adi_jesd204/adi_jesd204_hw.tcl @@ -147,7 +147,7 @@ proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} { } } -proc create_lane_pll {id pllclk_frequency refclk_frequency} { +proc create_lane_pll {id pllclk_frequency refclk_frequency num_lanes} { add_instance lane_pll altera_xcvr_atx_pll_a10 set_instance_property lane_pll SUPPRESS_ALL_INFO_MESSAGES true set_instance_parameter_value lane_pll {enable_pll_reconfig} {1} @@ -157,7 +157,18 @@ proc create_lane_pll {id pllclk_frequency refclk_frequency} { set_instance_parameter_value lane_pll {set_csr_soft_logic_enable} {1} set_instance_parameter_value lane_pll {set_output_clock_frequency} $pllclk_frequency set_instance_parameter_value lane_pll {set_auto_reference_clock_frequency} $refclk_frequency - add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown + if {$num_lanes > 6} { + set_instance_parameter_value lane_pll enable_mcgb {true} + set_instance_parameter_value lane_pll enable_hfreq_clk {true} + + add_instance glue adi_jesd204_glue + add_connection phy_reset_control.pll_powerdown glue.in_pll_powerdown + add_connection glue.out_pll_powerdown lane_pll.pll_powerdown + add_connection glue.out_mcgb_rst lane_pll.mcgb_rst + } else { + add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown + } + add_connection lane_pll.pll_locked phy_reset_control.pll_locked add_connection lane_pll.pll_cal_busy phy_reset_control.pll_cal_busy add_connection ref_clock.out_clk lane_pll.pll_refclk0 @@ -347,8 +358,11 @@ proc jesd204_compose {} { set jesd204_intfs {config control ilas_config event status} set phy_reset_intfs {analogreset digitalreset cal_busy} - create_lane_pll $id $pllclk_frequency $refclk_frequency - add_connection lane_pll.tx_serial_clk phy.serial_clk + create_lane_pll $id $pllclk_frequency $refclk_frequency $num_of_lanes + add_connection lane_pll.tx_serial_clk phy.serial_clk_x1 + if {$num_of_lanes > 6} { + add_connection lane_pll.mcgb_serial_clk phy.serial_clk_xN + } } else { set tx_rx "rx" set data_direction source diff --git a/library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl index 9204d7cab..e54f2aae6 100644 --- a/library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl +++ b/library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl @@ -131,6 +131,53 @@ proc glue_add_if_port {num ifname port role dir width {bcast false}} { set_port_property phy_${port} fragment_list $frag } +proc glue_add_tx_serial_clk {num_of_lanes} { + variable sig_offset + + # The serial clock is special. The first 6 transceivers use the x1 connection + # since they are in the same bank as the PLL. The others have to use the xN + # connection through the CGB. + + if {$num_of_lanes > 6} { + set clk0_width 6 + set clk1_width [expr $num_of_lanes - 6] + + } else { + set clk0_width $num_of_lanes + set clk1_width 0 + } + + add_interface tx_serial_clk_x1 hssi_serial_clock sink + add_interface_port tx_serial_clk_x1 tx_serial_clk_x1 clk Input 1 + set_port_property tx_serial_clk_x1 fragment_list \ + [format "in(%d:%d)" $sig_offset $sig_offset] + + add_interface phy_tx_serial_clk0 conduit end + add_interface_port phy_tx_serial_clk0 phy_tx_serial_clk0 clk Output $num_of_lanes + + set _frag [format "out(%d:%d)" $sig_offset $sig_offset] + set sig_offset [expr $sig_offset + 1] + set frag "${_frag}" + for {set i 1} {$i < $clk0_width} {incr i} { + set frag [concat ${_frag} ${frag}] + } + + if {$num_of_lanes > 6} { + add_interface tx_serial_clk_xN hssi_serial_clock sink + add_interface_port tx_serial_clk_xN tx_serial_clk_xN clk Input 1 + set_port_property tx_serial_clk_xN fragment_list \ + [format "in(%d:%d)" $sig_offset $sig_offset] + + set _frag [format "out(%d:%d)" $sig_offset $sig_offset] + set sig_offset [expr $sig_offset + 1] + for {set i 0} {$i < $clk1_width} {incr i} { + set frag [concat ${_frag} ${frag}] + } + } + + set_port_property phy_tx_serial_clk0 fragment_list $frag +} + proc glue_add_if_port_conduit {num ifname port phy_port dir width} { variable sig_offset @@ -209,9 +256,8 @@ proc jesd204_phy_glue_elab {} { glue_add_if $num_of_lanes tx_coreclkin clock sink true glue_add_if_port $num_of_lanes tx_coreclkin tx_coreclkin clk Input 1 true - glue_add_if $num_of_lanes tx_serial_clk0 hssi_serial_clock sink true - glue_add_if_port $num_of_lanes tx_serial_clk0 tx_serial_clk0 clk Input 1 true - + glue_add_tx_serial_clk $num_of_lanes + if {$soft_pcs} { set unused_width [expr $num_of_lanes * 88] diff --git a/library/altera/jesd204_phy/jesd204_phy_hw.tcl b/library/altera/jesd204_phy/jesd204_phy_hw.tcl index a4a8bc529..2656b5f6d 100644 --- a/library/altera/jesd204_phy/jesd204_phy_hw.tcl +++ b/library/altera/jesd204_phy/jesd204_phy_hw.tcl @@ -158,8 +158,13 @@ proc jesd204_phy_composition_callback {} { set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset if {$tx} { - add_interface serial_clk hssi_serial_clock end - set_interface_property serial_clk EXPORT_OF phy_glue.tx_serial_clk0 + add_interface serial_clk_x1 hssi_serial_clock end + set_interface_property serial_clk_x1 EXPORT_OF phy_glue.tx_serial_clk_x1 + + if {$num_of_lanes > 6} { + add_interface serial_clk_xN hssi_serial_clock end + set_interface_property serial_clk_xN EXPORT_OF phy_glue.tx_serial_clk_xN + } add_connection link_clock.clk phy_glue.tx_coreclkin