altera: adi_jesd204: Add support for more than 6 transmit lanes
On Arria10 there are 6 transceivers in a single bank. If more than 6 transceivers are used these will end up in multiple banks. The ATX PLL can directly connect to the transceivers in the same bank through the 1x clock network. To connect to transceivers in another bank it has to go through a master clock generation block (MCGB) and the xN clock network. Add support for instantiating the MCGB if more than 6 lanes are used. In this case the first 6 transceivers will still have a direct connection to the PLL while all other transceivers will be clocked by the MCGB. Note that this requires that the first 6 transceivers are all in the same bank. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
Adrian Costina
parent
a0309e3e3a
commit
29e6bbde88
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@ -5,6 +5,8 @@
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LIBRARY_NAME := adi_jesd204
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ALTERA_DEPS += adi_jesd204_glue.v
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ALTERA_DEPS += adi_jesd204_glue_hw.tcl
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ALTERA_DEPS += adi_jesd204_hw.tcl
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ALTERA_LIB_DEPS += altera/axi_adxcvr
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@ -0,0 +1,45 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module adi_jesd204_glue (
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input in_pll_powerdown,
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output out_pll_powerdown,
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output out_mcgb_rst
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);
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assign out_pll_powerdown = in_pll_powerdown;
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assign out_mcgb_rst = in_pll_powerdown;
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endmodule
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@ -0,0 +1,68 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
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# chips from Analog Devices, incorporate them into your PCB level product, and
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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package require qsys
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_alt.tcl
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ad_ip_create adi_jesd204_glue {Glue} jesd204_phy_glue_elab
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set_module_property INTERNAL true
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# files
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ad_ip_files adi_jesd204_glue [list \
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adi_jesd204_glue.v \
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]
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# parameters
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proc jesd204_phy_glue_elab {} {
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add_interface in_pll_powerdown conduit end
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add_interface_port in_pll_powerdown in_pll_powerdown pll_powerdown Input 1
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add_interface out_pll_powerdown conduit end
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add_interface_port out_pll_powerdown out_pll_powerdown pll_powerdown Output 1
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add_interface out_mcgb_rst conduit end
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add_interface_port out_mcgb_rst out_mcgb_rst mcgb_rst Output 1
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}
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@ -147,7 +147,7 @@ proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
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}
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}
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proc create_lane_pll {id pllclk_frequency refclk_frequency} {
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proc create_lane_pll {id pllclk_frequency refclk_frequency num_lanes} {
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add_instance lane_pll altera_xcvr_atx_pll_a10
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set_instance_property lane_pll SUPPRESS_ALL_INFO_MESSAGES true
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set_instance_parameter_value lane_pll {enable_pll_reconfig} {1}
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@ -157,7 +157,18 @@ proc create_lane_pll {id pllclk_frequency refclk_frequency} {
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set_instance_parameter_value lane_pll {set_csr_soft_logic_enable} {1}
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set_instance_parameter_value lane_pll {set_output_clock_frequency} $pllclk_frequency
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set_instance_parameter_value lane_pll {set_auto_reference_clock_frequency} $refclk_frequency
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add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown
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if {$num_lanes > 6} {
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set_instance_parameter_value lane_pll enable_mcgb {true}
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set_instance_parameter_value lane_pll enable_hfreq_clk {true}
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add_instance glue adi_jesd204_glue
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add_connection phy_reset_control.pll_powerdown glue.in_pll_powerdown
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add_connection glue.out_pll_powerdown lane_pll.pll_powerdown
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add_connection glue.out_mcgb_rst lane_pll.mcgb_rst
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} else {
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add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown
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}
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add_connection lane_pll.pll_locked phy_reset_control.pll_locked
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add_connection lane_pll.pll_cal_busy phy_reset_control.pll_cal_busy
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add_connection ref_clock.out_clk lane_pll.pll_refclk0
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@ -347,8 +358,11 @@ proc jesd204_compose {} {
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set jesd204_intfs {config control ilas_config event status}
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set phy_reset_intfs {analogreset digitalreset cal_busy}
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create_lane_pll $id $pllclk_frequency $refclk_frequency
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add_connection lane_pll.tx_serial_clk phy.serial_clk
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create_lane_pll $id $pllclk_frequency $refclk_frequency $num_of_lanes
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add_connection lane_pll.tx_serial_clk phy.serial_clk_x1
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if {$num_of_lanes > 6} {
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add_connection lane_pll.mcgb_serial_clk phy.serial_clk_xN
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}
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} else {
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set tx_rx "rx"
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set data_direction source
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@ -131,6 +131,53 @@ proc glue_add_if_port {num ifname port role dir width {bcast false}} {
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set_port_property phy_${port} fragment_list $frag
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}
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proc glue_add_tx_serial_clk {num_of_lanes} {
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variable sig_offset
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# The serial clock is special. The first 6 transceivers use the x1 connection
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# since they are in the same bank as the PLL. The others have to use the xN
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# connection through the CGB.
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if {$num_of_lanes > 6} {
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set clk0_width 6
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set clk1_width [expr $num_of_lanes - 6]
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} else {
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set clk0_width $num_of_lanes
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set clk1_width 0
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}
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add_interface tx_serial_clk_x1 hssi_serial_clock sink
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add_interface_port tx_serial_clk_x1 tx_serial_clk_x1 clk Input 1
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set_port_property tx_serial_clk_x1 fragment_list \
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[format "in(%d:%d)" $sig_offset $sig_offset]
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add_interface phy_tx_serial_clk0 conduit end
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add_interface_port phy_tx_serial_clk0 phy_tx_serial_clk0 clk Output $num_of_lanes
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set _frag [format "out(%d:%d)" $sig_offset $sig_offset]
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set sig_offset [expr $sig_offset + 1]
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set frag "${_frag}"
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for {set i 1} {$i < $clk0_width} {incr i} {
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set frag [concat ${_frag} ${frag}]
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}
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if {$num_of_lanes > 6} {
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add_interface tx_serial_clk_xN hssi_serial_clock sink
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add_interface_port tx_serial_clk_xN tx_serial_clk_xN clk Input 1
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set_port_property tx_serial_clk_xN fragment_list \
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[format "in(%d:%d)" $sig_offset $sig_offset]
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set _frag [format "out(%d:%d)" $sig_offset $sig_offset]
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set sig_offset [expr $sig_offset + 1]
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for {set i 0} {$i < $clk1_width} {incr i} {
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set frag [concat ${_frag} ${frag}]
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}
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}
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set_port_property phy_tx_serial_clk0 fragment_list $frag
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}
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proc glue_add_if_port_conduit {num ifname port phy_port dir width} {
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variable sig_offset
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@ -209,8 +256,7 @@ proc jesd204_phy_glue_elab {} {
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glue_add_if $num_of_lanes tx_coreclkin clock sink true
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glue_add_if_port $num_of_lanes tx_coreclkin tx_coreclkin clk Input 1 true
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glue_add_if $num_of_lanes tx_serial_clk0 hssi_serial_clock sink true
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glue_add_if_port $num_of_lanes tx_serial_clk0 tx_serial_clk0 clk Input 1 true
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glue_add_tx_serial_clk $num_of_lanes
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if {$soft_pcs} {
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set unused_width [expr $num_of_lanes * 88]
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@ -158,8 +158,13 @@ proc jesd204_phy_composition_callback {} {
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set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset
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if {$tx} {
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add_interface serial_clk hssi_serial_clock end
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set_interface_property serial_clk EXPORT_OF phy_glue.tx_serial_clk0
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add_interface serial_clk_x1 hssi_serial_clock end
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set_interface_property serial_clk_x1 EXPORT_OF phy_glue.tx_serial_clk_x1
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if {$num_of_lanes > 6} {
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add_interface serial_clk_xN hssi_serial_clock end
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set_interface_property serial_clk_xN EXPORT_OF phy_glue.tx_serial_clk_xN
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}
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add_connection link_clock.clk phy_glue.tx_coreclkin
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