axi_ad7616: Control inputs are controlled through GPIO

The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.

library/axi_ad7616/axi_ad7616.v

@@ -51,20 +51,14 @@ module axi_ad7616 (
 
   db_o,
   db_i,
+  db_t,
   rd_n,
   wr_n,
 
   // physical control interface
 
-  reset_n,
   cnvst,
   busy,
-  seq_en,
-  hw_rngsel,
-  chsel,
-  crcen,
-  burst,
-  os,
 
   // AXI Slave Memory Map
 
@@ -122,18 +116,12 @@ module axi_ad7616 (
 
   output  [15:0]  db_o;
   input   [15:0]  db_i;
+  output          db_t;
   output          rd_n;
   output          wr_n;
 
-  output          reset_n;
   output          cnvst;
   input           busy;
-  output          seq_en;
-  output  [ 1:0]  hw_rngsel;
-  output  [ 2:0]  chsel;
-  output          crcen;
-  output          burst;
-  output  [ 2:0]  os;
 
   input           s_axi_aclk;
   input           s_axi_aresetn;
@@ -419,15 +407,8 @@ module axi_ad7616 (
     .ID(ID),
     .OP_MODE (OP_MODE)
   ) i_ad7616_control (
-    .reset_n (reset_n),
     .cnvst (cnvst),
     .busy (busy),
-    .seq_en (seq_en),
-    .hw_rngsel (hw_rngsel),
-    .chsel (chsel),
-    .crcen (crcen),
-    .burst (burst),
-    .os (os),
     .end_of_conv (trigger_s),
     .up_rstn (up_rstn),
     .up_clk (up_clk),

library/axi_ad7616/axi_ad7616_control.v

@@ -43,15 +43,8 @@ module axi_ad7616_control (
 
   // control signals
 
-  reset_n,
   cnvst,
   busy,
-  seq_en,
-  hw_rngsel,
-  chsel,
-  crcen,
-  burst,
-  os,
 
   end_of_conv,
 
@@ -79,15 +72,8 @@ module axi_ad7616_control (
   localparam  POS_EDGE = 0;
   localparam  NEG_EDGE = 1;
 
-  output          reset_n;
   output          cnvst;
   input           busy;
-  output          seq_en;
-  output  [ 1:0]  hw_rngsel;
-  output  [ 2:0]  chsel;
-  output          crcen;
-  output          burst;
-  output  [ 2:0]  os;
 
   output          end_of_conv;
 
@@ -120,14 +106,6 @@ module axi_ad7616_control (
   reg             cnvst_pulse = 1'b0;
   reg     [ 2:0]  chsel_ff = 3'b0;
 
-  reg     [ 1:0]  up_hw_rngsel = 2'b0;
-  reg     [ 2:0]  up_chsel = 3'b0;
-  reg             up_crcen = 1'b0;
-  reg             up_burst = 1'b0;
-  reg     [ 2:0]  up_os = 3'b0;
-  reg             up_seq_en = 1'b0;
-
-
   wire            up_rst;
   wire            up_rreq_s;
   wire            up_wreq_s;
@@ -149,12 +127,6 @@ module axi_ad7616_control (
       up_resetn <= 1'b0;
       up_cnvst_en <= 1'b0;
       up_conv_rate <= 32'b0;
-      up_hw_rngsel <= 2'b0;
-      up_chsel <= 3'b0;
-      up_crcen <= 1'b0;
-      up_burst <= 1'b0;
-      up_os <= 3'b0;
-      up_seq_en <= 1'b0;
     end else begin
       up_wack <= up_wreq_s;
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@@ -167,18 +139,6 @@ module axi_ad7616_control (
       if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
         up_conv_rate <= up_wdata;
       end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
-        up_hw_rngsel <= up_wdata[1:0];
-        up_os <= up_wdata[4:2];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
-        up_seq_en <= up_wdata[0];
-        up_burst <= up_wdata[1];
-        up_chsel <= up_wdata[4:2];
-      end
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
-        up_crcen <= up_wdata[0];
-      end
     end
   end
 
@@ -197,9 +157,6 @@ module axi_ad7616_control (
             8'h02 : up_rdata = up_scratch;
             8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
             8'h11 : up_rdata = up_conv_rate;
-            8'h12 : up_rdata = {27'b0, up_os, up_hw_rngsel};
-            8'h13 : up_rdata = {27'b0, up_chsel, up_burst, up_seq_en};
-            8'h14 : up_rdata = {30'b0, up_crcen};
         endcase
       end
     end
@@ -252,45 +209,5 @@ module axi_ad7616_control (
 
   assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
 
-  // output logic
-
-  assign reset_n = up_resetn;       // device's reset
-
-  generate if (OP_MODE == SW) begin
-
-    // ground all the unused control signals
-
-    assign seq_en = 1'b0;
-    assign hw_rngsel = 2'b0;
-    assign chsel = 3'b0;
-    assign crcen = 1'b0;
-    assign burst = 1'b0;
-    assign os = 3'b0;
-
-  end
-  endgenerate
-
-  generate if (OP_MODE == HW) begin
-
-    assign hw_rngsel = up_hw_rngsel;
-    assign crcen = up_crcen;
-    assign burst = up_burst;
-    assign os = up_os;
-    assign seq_en = up_seq_en;
-    assign chsel = chsel_ff;
-
-    // CHSEL is updated after BUSY deasserts
-
-    always @(posedge up_clk) begin
-      if (up_rstn == 1'b0) begin
-        chsel_ff <= 3'b0;
-      end else begin
-        chsel_ff <= (end_of_conv_s == 1'b1) ? up_chsel : chsel_ff;
-      end
-    end
-
-  end
-  endgenerate
-
 endmodule
 

projects/ad7616_sdz/common/ad7616_bd.tcl

@@ -16,16 +16,9 @@ create_bd_port -dir O wr_n
 
 # control lines
 
-create_bd_port -dir O reset_n
 create_bd_port -dir O cnvst
 create_bd_port -dir O cs_n
 create_bd_port -dir I busy
-create_bd_port -dir O seq_en
-create_bd_port -dir O -from 1 -to 0 hw_rngsel
-create_bd_port -dir O -from 2 -to 0 chsel
-create_bd_port -dir O crcen
-create_bd_port -dir O burst
-create_bd_port -dir O -from 2 -to 0 os
 
 # instantiation
 
@@ -50,15 +43,8 @@ if {$ad7616_if == 0} {
   ad_connect  sdi_1 axi_ad7616/sdi_1
   ad_connect  cs_n axi_ad7616/cs_n
 
-  ad_connect  reset_n axi_ad7616/reset_n
   ad_connect  cnvst axi_ad7616/cnvst
   ad_connect  busy axi_ad7616/busy
-  ad_connect  seq_en axi_ad7616/seq_en
-  ad_connect  hw_rngsel axi_ad7616/hw_rngsel
-  ad_connect  chsel axi_ad7616/chsel
-  ad_connect  crcen axi_ad7616/crcen
-  ad_connect  burst axi_ad7616/burst
-  ad_connect  os axi_ad7616/os
 
 } else {
 

projects/ad7616_sdz/zc706/system_top.v

@@ -153,6 +153,18 @@ module system_top (
 
   // instantiations
 
+  ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
+    .dio_t (gpio_t[43:32]),
+    .dio_i (gpio_o[43:32]),
+    .dio_o (gpio_i[43:32]),
+    .dio_p ({adc_reset_n,        // 43
+             adc_hw_rngsel,      // 42:41
+             adc_os,             // 40:38
+             adc_seq_en,         // 37
+             adc_burst,          // 36
+             adc_chsel,          // 35:33
+             adc_crcen}));       // 32
+
   ad_iobuf #(
     .DATA_WIDTH(15)
   ) i_gpio_bd (
@@ -210,16 +222,9 @@ module system_top (
     .sdo (spi_sdo),
     .sdi_0 (spi_sdi_0),
     .sdi_1 (spi_sdi_1),
-    .reset_n (adc_reset_n),
     .cnvst (adc_convst),
     .cs_n (spi_cs_n),
-    .busy (adc_busy),
+    .busy (adc_busy));
-    .seq_en (adc_seq_en),
-    .hw_rngsel (adc_hw_rngsel),
-    .chsel (adc_chsel),
-    .crcen (adc_crcen),
-    .burst (adc_burst),
-    .os (adc_os));
 
 endmodule