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jesd204: Add constraints for the rx statistics clock crossing

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Adrian Costina 2018-05-10 16:32:50 +03:00
parent 3b9f733408
commit 2aa3b77a9c
1 changed files with 13 additions and 0 deletions
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13
library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
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@ -64,6 +64,14 @@ set_false_path \
-from [get_pins {i_up_rx/i_cdc_status/out_toggle_d1_reg/C}] \ -from [get_pins {i_up_rx/i_cdc_status/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_rx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_rx/i_cdc_cfg/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_cdc_cfg/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_rx/i_cdc_cfg/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_cdc_cfg/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \ -from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}]
@ -86,6 +94,11 @@ set_false_path \
-from $core_clk \ -from $core_clk \
-to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}] -to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}]
set_max_delay -datapath_only \
-from [get_pins {i_up_rx/i_cdc_cfg/cdc_hold_reg[*]/C}] \
-to [get_pins {i_up_rx/i_cdc_cfg/out_data_reg[*]/D}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from $core_clk \ -from $core_clk \
-to [get_pins {i_up_rx/*i_up_rx_lane/up_status_latency_reg[*]/D}] \ -to [get_pins {i_up_rx/*i_up_rx_lane/up_status_latency_reg[*]/D}] \