From 2ae09c98081383b0375e0f460d8698df18ace8bb Mon Sep 17 00:00:00 2001 From: laurent-19 Date: Thu, 23 Mar 2023 14:10:43 +0200 Subject: [PATCH] Check guidelines. Remove redundancies * Removed empty/commented lines * Regenerated Makefiles * Removed redundancies adc channels data width * Set data width 32-bit: max resolution and CRC header Signed-off-by: laurent-19 --- library/spi_engine/scripts/spi_engine.tcl | 6 ------ projects/ad4134_fmc/Makefile | 2 +- projects/ad4134_fmc/common/ad4134_bd.tcl | 14 +++----------- projects/ad4134_fmc/zed/Makefile | 2 +- projects/ad4134_fmc/zed/system_bd.tcl | 9 --------- projects/ad4134_fmc/zed/system_constr.xdc | 1 - projects/ad4134_fmc/zed/system_project.tcl | 2 -- projects/ad4630_fmc/common/ad463x_bd.tcl | 6 ------ projects/ad4630_fmc/zed/system_bd.tcl | 1 - projects/ad4630_fmc/zed/system_constr.xdc | 2 -- projects/ad4630_fmc/zed/system_constr_1sdi.xdc | 2 -- projects/ad4630_fmc/zed/system_constr_2sdi.xdc | 2 -- projects/ad4630_fmc/zed/system_constr_4sdi.xdc | 2 -- projects/ad4630_fmc/zed/system_constr_8sdi.xdc | 2 -- projects/ad4630_fmc/zed/system_project.tcl | 1 - projects/ad469x_fmc/common/ad469x_bd.tcl | 1 - projects/ad469x_fmc/zed/system_bd.tcl | 1 - projects/ad469x_fmc/zed/system_constr.xdc | 1 - projects/ad7134_fmc/common/ad7134_bd.tcl | 14 ++++---------- projects/ad7134_fmc/zed/Makefile | 1 + projects/ad7134_fmc/zed/system_bd.tcl | 9 --------- projects/ad7134_fmc/zed/system_constr.xdc | 1 - projects/ad7134_fmc/zed/system_project.tcl | 1 - projects/cn0561/common/cn0561_bd.tcl | 15 +++------------ projects/cn0561/coraz7s/Makefile | 1 + projects/cn0561/coraz7s/system_bd.tcl | 9 --------- projects/cn0561/zed/Makefile | 2 +- projects/cn0561/zed/system_bd.tcl | 8 -------- projects/cn0561/zed/system_constr.xdc | 1 - projects/cn0561/zed/system_project.tcl | 1 - .../pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl | 1 - projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl | 1 - .../pulsar_adc_pmdz/coraz7s/system_constr.xdc | 2 -- .../pulsar_adc_pmdz/coraz7s/system_project.tcl | 1 - 34 files changed, 15 insertions(+), 110 deletions(-) diff --git a/library/spi_engine/scripts/spi_engine.tcl b/library/spi_engine/scripts/spi_engine.tcl index 941b30c4c..9ff944144 100644 --- a/library/spi_engine/scripts/spi_engine.tcl +++ b/library/spi_engine/scripts/spi_engine.tcl @@ -1,6 +1,5 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0}} { - puts "echo_sclk: $echo_sclk" create_bd_cell -type hier $name @@ -18,8 +17,6 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n create_bd_pin -dir O irq create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample -# create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_sample_0 -# create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_sample_1 set execution "${name}_execution" set axi_regmap "${name}_axi_regmap" @@ -30,7 +27,6 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi -# ad_ip_parameter $execution CONFIG.NUM_OF_SDO $num_sdo ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1 ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk @@ -55,8 +51,6 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl ad_connect $interconnect/m_ctrl $execution/ctrl ad_connect $offload/offload_sdi m_axis_sample -# ad_connect $offload/offload_sdo_0 s_axis_sample_0 -# ad_connect $offload/offload_sdo_1 s_axis_sample_1 ad_connect $offload/trigger trigger ad_connect $execution/spi m_spi diff --git a/projects/ad4134_fmc/Makefile b/projects/ad4134_fmc/Makefile index 2458d9876..1402069e1 100644 --- a/projects/ad4134_fmc/Makefile +++ b/projects/ad4134_fmc/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2021 Analog Devices, Inc. +## Copyright (c) 2018 - 2023 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad4134_fmc/common/ad4134_bd.tcl b/projects/ad4134_fmc/common/ad4134_bd.tcl index a4166bbcb..55675ddc8 100644 --- a/projects/ad4134_fmc/common/ad4134_bd.tcl +++ b/projects/ad4134_fmc/common/ad4134_bd.tcl @@ -1,4 +1,3 @@ - create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad4134_di create_bd_port -dir O ad4134_odr @@ -6,17 +5,10 @@ create_bd_port -dir O ad4134_odr source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl -if {$adc_resolution == 16} { - set data_width 24 -} elseif {$adc_resolution == 24} { - set data_width 32 -} elseif {$adc_resolution == 32} { - set data_width 64 -}; - +set data_width 32 set async_spi_clk 1 set num_cs 1 -set num_sdi $adc_num_of_channels +set num_sdi 4 set num_sdo 0 set sdi_delay 0 set echo_sclk 0 @@ -40,7 +32,7 @@ ad_ip_parameter axi_ad4134_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_ad4134_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_ad4134_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ad4134_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels] +ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_DEST 64 # odr generator diff --git a/projects/ad4134_fmc/zed/Makefile b/projects/ad4134_fmc/zed/Makefile index f2f6de174..c8a14a61b 100755 --- a/projects/ad4134_fmc/zed/Makefile +++ b/projects/ad4134_fmc/zed/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2021 Analog Devices, Inc. +## Copyright (c) 2018 - 2023 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/projects/ad4134_fmc/zed/system_bd.tcl b/projects/ad4134_fmc/zed/system_bd.tcl index 6037a77f0..48d433025 100755 --- a/projects/ad4134_fmc/zed/system_bd.tcl +++ b/projects/ad4134_fmc/zed/system_bd.tcl @@ -1,4 +1,3 @@ - source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl @@ -9,12 +8,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file -# specify ADC resolution -- the design supports 16/24/32 bit resolutions - -set adc_resolution 24 - -# ADC number of channels - -set adc_num_of_channels 4 - source ../common/ad4134_bd.tcl diff --git a/projects/ad4134_fmc/zed/system_constr.xdc b/projects/ad4134_fmc/zed/system_constr.xdc index 1b4f32e92..d8052a2d4 100755 --- a/projects/ad4134_fmc/zed/system_constr.xdc +++ b/projects/ad4134_fmc/zed/system_constr.xdc @@ -1,4 +1,3 @@ - # ad4134 SPI configuration interface set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdi] ; ## FMC_LPC_LA03_P diff --git a/projects/ad4134_fmc/zed/system_project.tcl b/projects/ad4134_fmc/zed/system_project.tcl index 760947b9c..6d3bd8535 100755 --- a/projects/ad4134_fmc/zed/system_project.tcl +++ b/projects/ad4134_fmc/zed/system_project.tcl @@ -1,4 +1,3 @@ - source ../../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -12,4 +11,3 @@ adi_project_files ad4134_fmc_zed [list \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] adi_project_run ad4134_fmc_zed - diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl index 2d953907a..175721f07 100644 --- a/projects/ad4630_fmc/common/ad463x_bd.tcl +++ b/projects/ad4630_fmc/common/ad463x_bd.tcl @@ -1,4 +1,3 @@ - source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl # system level parameters @@ -40,7 +39,6 @@ ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8 ad_connect $sys_cpu_clk spi_clkgen/clk ad_connect spi_clk spi_clkgen/clk_0 - # create a SPI Engine architecture #spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDI 0 1 @@ -57,9 +55,6 @@ set hier_spi_engine spi_ad463x spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk - - - ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_execution CONFIG.DEFAULT_SPI_CFG 1 ; # latching MISO on negative edge - hardware only ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI @@ -214,4 +209,3 @@ ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect sys_cpu_clk axi_ad463x_dma/m_dest_axi - diff --git a/projects/ad4630_fmc/zed/system_bd.tcl b/projects/ad4630_fmc/zed/system_bd.tcl index ad4715d71..f488ddae9 100644 --- a/projects/ad4630_fmc/zed/system_bd.tcl +++ b/projects/ad4630_fmc/zed/system_bd.tcl @@ -17,4 +17,3 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 set sys_cstring "sys rom custom string placeholder" sysid_gen_sys_init_file $sys_cstring - diff --git a/projects/ad4630_fmc/zed/system_constr.xdc b/projects/ad4630_fmc/zed/system_constr.xdc index da5035e4c..78a4e3f68 100644 --- a/projects/ad4630_fmc/zed/system_constr.xdc +++ b/projects/ad4630_fmc/zed/system_constr.xdc @@ -1,4 +1,3 @@ - # ad463x_fmc SPI interface set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] @@ -36,4 +35,3 @@ set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchic set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_execution/inst/left_aligned_reg*] 8 set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_execution/inst/left_aligned_reg*] 7 - diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi.xdc index 39b64b583..1d72acc92 100644 --- a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc +++ b/projects/ad4630_fmc/zed/system_constr_1sdi.xdc @@ -1,4 +1,3 @@ - set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P # input delays for MISO lines (SDO for the device) @@ -9,4 +8,3 @@ set thold 1.4 set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi] - diff --git a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi.xdc index 364667fc5..7e23a9060 100644 --- a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc +++ b/projects/ad4630_fmc/zed/system_constr_2sdi.xdc @@ -1,4 +1,3 @@ - set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P @@ -12,4 +11,3 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] - diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi.xdc index cac5c7c14..26f527d21 100644 --- a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc +++ b/projects/ad4630_fmc/zed/system_constr_4sdi.xdc @@ -1,4 +1,3 @@ - set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] @@ -18,4 +17,3 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_p set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}] - diff --git a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc b/projects/ad4630_fmc/zed/system_constr_8sdi.xdc index a07383a71..f2e5c537b 100644 --- a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc +++ b/projects/ad4630_fmc/zed/system_constr_8sdi.xdc @@ -1,4 +1,3 @@ - set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P @@ -28,4 +27,3 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]] - diff --git a/projects/ad4630_fmc/zed/system_project.tcl b/projects/ad4630_fmc/zed/system_project.tcl index c29a46697..794618cad 100644 --- a/projects/ad4630_fmc/zed/system_project.tcl +++ b/projects/ad4630_fmc/zed/system_project.tcl @@ -80,4 +80,3 @@ switch [get_env_param NUM_OF_SDI 4] { } adi_project_run ad4630_fmc_zed - diff --git a/projects/ad469x_fmc/common/ad469x_bd.tcl b/projects/ad469x_fmc/common/ad469x_bd.tcl index c70ce6f63..825cc003c 100644 --- a/projects/ad469x_fmc/common/ad469x_bd.tcl +++ b/projects/ad469x_fmc/common/ad469x_bd.tcl @@ -1,4 +1,3 @@ - create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad469x_spi create_bd_port -dir O ad469x_spi_cnv create_bd_port -dir I ad469x_spi_busy diff --git a/projects/ad469x_fmc/zed/system_bd.tcl b/projects/ad469x_fmc/zed/system_bd.tcl index d8656a31e..a99776f61 100644 --- a/projects/ad469x_fmc/zed/system_bd.tcl +++ b/projects/ad469x_fmc/zed/system_bd.tcl @@ -25,4 +25,3 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file - diff --git a/projects/ad469x_fmc/zed/system_constr.xdc b/projects/ad469x_fmc/zed/system_constr.xdc index 0d0d0c09a..b38ab6939 100644 --- a/projects/ad469x_fmc/zed/system_constr.xdc +++ b/projects/ad469x_fmc/zed/system_constr.xdc @@ -1,4 +1,3 @@ - # ad4696_fmc SPI interface set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P diff --git a/projects/ad7134_fmc/common/ad7134_bd.tcl b/projects/ad7134_fmc/common/ad7134_bd.tcl index 416748332..380e5229f 100644 --- a/projects/ad7134_fmc/common/ad7134_bd.tcl +++ b/projects/ad7134_fmc/common/ad7134_bd.tcl @@ -1,4 +1,3 @@ - create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad713x_di create_bd_port -dir O ad713x_odr create_bd_port -dir O ad713x_sdpclk @@ -7,16 +6,11 @@ create_bd_port -dir O ad713x_sdpclk # this design supports AD7132/AD7134/AD7136 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl - -if {$adc_resolution == 16 || $adc_resolution == 24} { - set data_width 32 -} elseif {$adc_resolution == 32} { - set data_width 64 -}; - + +set data_width 32 set async_spi_clk 1 set num_cs 1 -set num_sdi $adc_num_of_channels +set num_sdi 8 set num_sdo 0 set sdi_delay 0 set echo_sclk 0 @@ -42,7 +36,7 @@ ad_ip_parameter axi_ad7134_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_ad7134_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels] +ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC 256 ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_DEST 128 # odr generator diff --git a/projects/ad7134_fmc/zed/Makefile b/projects/ad7134_fmc/zed/Makefile index ade91e852..f89879abb 100644 --- a/projects/ad7134_fmc/zed/Makefile +++ b/projects/ad7134_fmc/zed/Makefile @@ -11,6 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/ad7134_fmc/zed/system_bd.tcl b/projects/ad7134_fmc/zed/system_bd.tcl index b03e3fceb..a32a9ccbd 100644 --- a/projects/ad7134_fmc/zed/system_bd.tcl +++ b/projects/ad7134_fmc/zed/system_bd.tcl @@ -15,13 +15,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file -# specify ADC resolution -- the design supports 16/24/32 bit resolutions - -set adc_resolution 24 - -# ADC number of channels - -set adc_num_of_channels 8 - - source ../common/ad7134_bd.tcl diff --git a/projects/ad7134_fmc/zed/system_constr.xdc b/projects/ad7134_fmc/zed/system_constr.xdc index 075286adc..24ddae262 100644 --- a/projects/ad7134_fmc/zed/system_constr.xdc +++ b/projects/ad7134_fmc/zed/system_constr.xdc @@ -1,4 +1,3 @@ - # ad713x SPI configuration interface set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdi] ; ## FMC_LPC_LA03_P diff --git a/projects/ad7134_fmc/zed/system_project.tcl b/projects/ad7134_fmc/zed/system_project.tcl index db19f29b9..e6e52aa0e 100644 --- a/projects/ad7134_fmc/zed/system_project.tcl +++ b/projects/ad7134_fmc/zed/system_project.tcl @@ -11,4 +11,3 @@ adi_project_files ad7134_fmc_zed [list \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] adi_project_run ad7134_fmc_zed - diff --git a/projects/cn0561/common/cn0561_bd.tcl b/projects/cn0561/common/cn0561_bd.tcl index 0855d8c80..6538213f3 100644 --- a/projects/cn0561/common/cn0561_bd.tcl +++ b/projects/cn0561/common/cn0561_bd.tcl @@ -1,4 +1,3 @@ - create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 cn0561_di create_bd_port -dir O cn0561_odr @@ -6,17 +5,10 @@ create_bd_port -dir O cn0561_odr source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl -if {$adc_resolution == 16} { - set data_width 24 -} elseif {$adc_resolution == 24} { - set data_width 32 -} elseif {$adc_resolution == 32} { - set data_width 64 -}; - +set data_width 32 set async_spi_clk 1 set num_cs 1 -set num_sdi $adc_num_of_channels +set num_sdi 4 set num_sdo 0 set sdi_delay 0 set echo_sclk 0 @@ -40,7 +32,7 @@ ad_ip_parameter axi_cn0561_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_cn0561_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_cn0561_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_cn0561_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels] +ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_DEST 64 # odr generator @@ -57,7 +49,6 @@ ad_connect odr_generator/ext_clk axi_cn0561_clkgen/clk_0 ad_connect odr_generator/pwm_0 $hier_spi_engine/trigger ad_connect odr_generator/pwm_1 cn0561_odr - ad_connect axi_cn0561_clkgen/clk_0 $hier_spi_engine/spi_clk ad_connect $sys_cpu_clk axi_cn0561_clkgen/clk ad_connect $sys_cpu_clk $hier_spi_engine/clk diff --git a/projects/cn0561/coraz7s/Makefile b/projects/cn0561/coraz7s/Makefile index 9b40adb65..55ffe32f2 100644 --- a/projects/cn0561/coraz7s/Makefile +++ b/projects/cn0561/coraz7s/Makefile @@ -12,6 +12,7 @@ M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v diff --git a/projects/cn0561/coraz7s/system_bd.tcl b/projects/cn0561/coraz7s/system_bd.tcl index 60fc54e91..14567184a 100644 --- a/projects/cn0561/coraz7s/system_bd.tcl +++ b/projects/cn0561/coraz7s/system_bd.tcl @@ -23,13 +23,4 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_I2C0_IO EMIO ad_connect iic_0_io sys_ps7/IIC_0 -# specify ADC resolution -- the design supports 16/24/32 bit resolutions - -set adc_resolution 24 - -# ADC number of channels - -set adc_num_of_channels 4 - source ../common/cn0561_bd.tcl - diff --git a/projects/cn0561/zed/Makefile b/projects/cn0561/zed/Makefile index 1289726e5..0d86cac13 100755 --- a/projects/cn0561/zed/Makefile +++ b/projects/cn0561/zed/Makefile @@ -11,9 +11,9 @@ M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_edge_detect.v -M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac diff --git a/projects/cn0561/zed/system_bd.tcl b/projects/cn0561/zed/system_bd.tcl index 7cf4e0a95..d8bb0c7f8 100755 --- a/projects/cn0561/zed/system_bd.tcl +++ b/projects/cn0561/zed/system_bd.tcl @@ -15,12 +15,4 @@ adi_project_files cn0561_fmc_zed [list \ sysid_gen_sys_init_file -# specify ADC resolution -- the design supports 16/24/32 bit resolutions - -set adc_resolution 24 - -# ADC number of channels - -set adc_num_of_channels 4 - source ../common/cn0561_bd.tcl diff --git a/projects/cn0561/zed/system_constr.xdc b/projects/cn0561/zed/system_constr.xdc index 8252442a4..14a36fe6c 100755 --- a/projects/cn0561/zed/system_constr.xdc +++ b/projects/cn0561/zed/system_constr.xdc @@ -1,4 +1,3 @@ - # cn0561 SPI configuration interface set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sdi] ; ## FMC_LPC_LA03_P diff --git a/projects/cn0561/zed/system_project.tcl b/projects/cn0561/zed/system_project.tcl index ccc532a77..0a6b35ced 100755 --- a/projects/cn0561/zed/system_project.tcl +++ b/projects/cn0561/zed/system_project.tcl @@ -11,4 +11,3 @@ adi_project_files cn0561_zed [list \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] adi_project_run cn0561_zed - diff --git a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl b/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl index d0d05a51a..5c005da8c 100644 --- a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl +++ b/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl @@ -1,4 +1,3 @@ - create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 pulsar_adc_spi source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl b/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl index 293728278..037acfadf 100644 --- a/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl +++ b/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl @@ -10,4 +10,3 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"; ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file - diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc b/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc index 6a3aaf2d2..39cdbd99d 100644 --- a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc +++ b/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc @@ -1,4 +1,3 @@ - # ad40xx_fmc SPI interface set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo] ; ## PMOD JA [2] @@ -17,4 +16,3 @@ set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_ set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] - diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl b/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl index 0e930ee52..14c544f42 100755 --- a/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl +++ b/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl @@ -11,4 +11,3 @@ adi_project_files pulsar_adc_pmdz_coraz7s [list \ "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"] adi_project_run pulsar_adc_pmdz_coraz7s -