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Check guidelines. Remove redundancies 

* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
main
laurent-19 2023-03-23 14:10:43 +02:00 committed by laurent-19
parent 1bef2bf304
commit 2ae09c9808
34 changed files with 15 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
library/spi_engine/scripts/spi_engine.tcl
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@ -1,6 +1,5 @@
proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0}} { proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0}} {
puts "echo_sclk: $echo_sclk" puts "echo_sclk: $echo_sclk"
create_bd_cell -type hier $name create_bd_cell -type hier $name
@ -18,8 +17,6 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
create_bd_pin -dir O irq create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
# create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_sample_0
# create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_sample_1
set execution "${name}_execution" set execution "${name}_execution"
set axi_regmap "${name}_axi_regmap" set axi_regmap "${name}_axi_regmap"
@ -30,7 +27,6 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width
ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs
ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi
# ad_ip_parameter $execution CONFIG.NUM_OF_SDO $num_sdo
ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1 ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1
ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay
ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk
@ -55,8 +51,6 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
ad_connect $interconnect/m_ctrl $execution/ctrl ad_connect $interconnect/m_ctrl $execution/ctrl
ad_connect $offload/offload_sdi m_axis_sample ad_connect $offload/offload_sdi m_axis_sample
# ad_connect $offload/offload_sdo_0 s_axis_sample_0
# ad_connect $offload/offload_sdo_1 s_axis_sample_1
ad_connect $offload/trigger trigger ad_connect $offload/trigger trigger
ad_connect $execution/spi m_spi ad_connect $execution/spi m_spi

2
projects/ad4134_fmc/Makefile
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@ -1,5 +1,5 @@
#################################################################################### ####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc. ## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause ### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify! ## Auto-generated, do not modify!
#################################################################################### ####################################################################################

14
projects/ad4134_fmc/common/ad4134_bd.tcl
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@ -1,4 +1,3 @@
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad4134_di create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad4134_di
create_bd_port -dir O ad4134_odr create_bd_port -dir O ad4134_odr
@ -6,17 +5,10 @@ create_bd_port -dir O ad4134_odr
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
if {$adc_resolution == 16} { set data_width 32
set data_width 24
} elseif {$adc_resolution == 24} {
set data_width 32
} elseif {$adc_resolution == 32} {
set data_width 64
};
set async_spi_clk 1 set async_spi_clk 1
set num_cs 1 set num_cs 1
set num_sdi $adc_num_of_channels set num_sdi 4
set num_sdo 0 set num_sdo 0
set sdi_delay 0 set sdi_delay 0
set echo_sclk 0 set echo_sclk 0
@ -40,7 +32,7 @@ ad_ip_parameter axi_ad4134_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad4134_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_ad4134_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad4134_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ad4134_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad4134_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad4134_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels] ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_DEST 64
# odr generator # odr generator

2
projects/ad4134_fmc/zed/Makefile
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@ -1,5 +1,5 @@
#################################################################################### ####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc. ## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause ### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify! ## Auto-generated, do not modify!
#################################################################################### ####################################################################################

9
projects/ad4134_fmc/zed/system_bd.tcl
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@ -1,4 +1,3 @@
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl
@ -9,12 +8,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file sysid_gen_sys_init_file
# specify ADC resolution -- the design supports 16/24/32 bit resolutions
set adc_resolution 24
# ADC number of channels
set adc_num_of_channels 4
source ../common/ad4134_bd.tcl source ../common/ad4134_bd.tcl

1
projects/ad4134_fmc/zed/system_constr.xdc
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@ -1,4 +1,3 @@
# ad4134 SPI configuration interface # ad4134 SPI configuration interface
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdi] ; ## FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdi] ; ## FMC_LPC_LA03_P

2
projects/ad4134_fmc/zed/system_project.tcl
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@ -1,4 +1,3 @@
source ../../../scripts/adi_env.tcl source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
@ -12,4 +11,3 @@ adi_project_files ad4134_fmc_zed [list \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run ad4134_fmc_zed adi_project_run ad4134_fmc_zed

6
projects/ad4630_fmc/common/ad463x_bd.tcl
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@ -1,4 +1,3 @@
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
# system level parameters # system level parameters
@ -40,7 +39,6 @@ ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
ad_connect $sys_cpu_clk spi_clkgen/clk ad_connect $sys_cpu_clk spi_clkgen/clk
ad_connect spi_clk spi_clkgen/clk_0 ad_connect spi_clk spi_clkgen/clk_0
# create a SPI Engine architecture # create a SPI Engine architecture
#spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDI 0 1 #spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDI 0 1
@ -57,9 +55,6 @@ set hier_spi_engine spi_ad463x
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_execution CONFIG.DEFAULT_SPI_CFG 1 ; # latching MISO on negative edge - hardware only ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_execution CONFIG.DEFAULT_SPI_CFG 1 ; # latching MISO on negative edge - hardware only
ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI
@ -214,4 +209,3 @@ ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad463x_dma/m_dest_axi ad_mem_hp2_interconnect sys_cpu_clk axi_ad463x_dma/m_dest_axi

1
projects/ad4630_fmc/zed/system_bd.tcl
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@ -17,4 +17,3 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "sys rom custom string placeholder" set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring sysid_gen_sys_init_file $sys_cstring

2
projects/ad4630_fmc/zed/system_constr.xdc
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@ -1,4 +1,3 @@
# ad463x_fmc SPI interface # ad463x_fmc SPI interface
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo]
@ -36,4 +35,3 @@ set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchic
set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_execution/inst/left_aligned_reg*] 8 set_multicycle_path -setup -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_execution/inst/left_aligned_reg*] 8
set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_execution/inst/left_aligned_reg*] 7 set_multicycle_path -hold -from [get_clocks spi_clk] -to [get_cells -hierarchical -filter NAME=~*/spi_ad463x_execution/inst/left_aligned_reg*] 7

2
projects/ad4630_fmc/zed/system_constr_1sdi.xdc
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@ -1,4 +1,3 @@
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P
# input delays for MISO lines (SDO for the device) # input delays for MISO lines (SDO for the device)
@ -9,4 +8,3 @@ set thold 1.4
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi]

2
projects/ad4630_fmc/zed/system_constr_2sdi.xdc
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@ -1,4 +1,3 @@
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P
@ -12,4 +11,3 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]]

2
projects/ad4630_fmc/zed/system_constr_4sdi.xdc
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@ -1,4 +1,3 @@
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}]
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}]
@ -18,4 +17,3 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_p
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[2]}]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[3]}]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[3]}]

2
projects/ad4630_fmc/zed/system_constr_8sdi.xdc
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@ -1,4 +1,3 @@
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P
@ -28,4 +27,3 @@ set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[6]]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[7]]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]] set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[7]]

1
projects/ad4630_fmc/zed/system_project.tcl
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@ -80,4 +80,3 @@ switch [get_env_param NUM_OF_SDI 4] {
} }
adi_project_run ad4630_fmc_zed adi_project_run ad4630_fmc_zed

1
projects/ad469x_fmc/common/ad469x_bd.tcl
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@ -1,4 +1,3 @@
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad469x_spi create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad469x_spi
create_bd_port -dir O ad469x_spi_cnv create_bd_port -dir O ad469x_spi_cnv
create_bd_port -dir I ad469x_spi_busy create_bd_port -dir I ad469x_spi_busy

1
projects/ad469x_fmc/zed/system_bd.tcl
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@ -25,4 +25,3 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file sysid_gen_sys_init_file

1
projects/ad469x_fmc/zed/system_constr.xdc
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@ -1,4 +1,3 @@
# ad4696_fmc SPI interface # ad4696_fmc SPI interface
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P

14
projects/ad7134_fmc/common/ad7134_bd.tcl
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@ -1,4 +1,3 @@
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad713x_di create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad713x_di
create_bd_port -dir O ad713x_odr create_bd_port -dir O ad713x_odr
create_bd_port -dir O ad713x_sdpclk create_bd_port -dir O ad713x_sdpclk
@ -7,16 +6,11 @@ create_bd_port -dir O ad713x_sdpclk
# this design supports AD7132/AD7134/AD7136 # this design supports AD7132/AD7134/AD7136
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
if {$adc_resolution == 16 || $adc_resolution == 24} { set data_width 32
set data_width 32
} elseif {$adc_resolution == 32} {
set data_width 64
};
set async_spi_clk 1 set async_spi_clk 1
set num_cs 1 set num_cs 1
set num_sdi $adc_num_of_channels set num_sdi 8
set num_sdo 0 set num_sdo 0
set sdi_delay 0 set sdi_delay 0
set echo_sclk 0 set echo_sclk 0
@ -42,7 +36,7 @@ ad_ip_parameter axi_ad7134_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad7134_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels] ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC 256
ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_DEST 128
# odr generator # odr generator

1
projects/ad7134_fmc/zed/Makefile
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@ -11,6 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v M_DEPS += ../../../library/common/ad_edge_detect.v

9
projects/ad7134_fmc/zed/system_bd.tcl
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@ -15,13 +15,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file sysid_gen_sys_init_file
# specify ADC resolution -- the design supports 16/24/32 bit resolutions
set adc_resolution 24
# ADC number of channels
set adc_num_of_channels 8
source ../common/ad7134_bd.tcl source ../common/ad7134_bd.tcl

1
projects/ad7134_fmc/zed/system_constr.xdc
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@ -1,4 +1,3 @@
# ad713x SPI configuration interface # ad713x SPI configuration interface
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdi] ; ## FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdi] ; ## FMC_LPC_LA03_P

1
projects/ad7134_fmc/zed/system_project.tcl
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@ -11,4 +11,3 @@ adi_project_files ad7134_fmc_zed [list \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run ad7134_fmc_zed adi_project_run ad7134_fmc_zed

15
projects/cn0561/common/cn0561_bd.tcl
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@ -1,4 +1,3 @@
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 cn0561_di create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 cn0561_di
create_bd_port -dir O cn0561_odr create_bd_port -dir O cn0561_odr
@ -6,17 +5,10 @@ create_bd_port -dir O cn0561_odr
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
if {$adc_resolution == 16} { set data_width 32
set data_width 24
} elseif {$adc_resolution == 24} {
set data_width 32
} elseif {$adc_resolution == 32} {
set data_width 64
};
set async_spi_clk 1 set async_spi_clk 1
set num_cs 1 set num_cs 1
set num_sdi $adc_num_of_channels set num_sdi 4
set num_sdo 0 set num_sdo 0
set sdi_delay 0 set sdi_delay 0
set echo_sclk 0 set echo_sclk 0
@ -40,7 +32,7 @@ ad_ip_parameter axi_cn0561_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_cn0561_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_cn0561_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_cn0561_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_cn0561_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_cn0561_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_cn0561_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels] ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_ip_parameter axi_cn0561_dma CONFIG.DMA_DATA_WIDTH_DEST 64
# odr generator # odr generator
@ -57,7 +49,6 @@ ad_connect odr_generator/ext_clk axi_cn0561_clkgen/clk_0
ad_connect odr_generator/pwm_0 $hier_spi_engine/trigger ad_connect odr_generator/pwm_0 $hier_spi_engine/trigger
ad_connect odr_generator/pwm_1 cn0561_odr ad_connect odr_generator/pwm_1 cn0561_odr
ad_connect axi_cn0561_clkgen/clk_0 $hier_spi_engine/spi_clk ad_connect axi_cn0561_clkgen/clk_0 $hier_spi_engine/spi_clk
ad_connect $sys_cpu_clk axi_cn0561_clkgen/clk ad_connect $sys_cpu_clk axi_cn0561_clkgen/clk
ad_connect $sys_cpu_clk $hier_spi_engine/clk ad_connect $sys_cpu_clk $hier_spi_engine/clk

1
projects/cn0561/coraz7s/Makefile
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@ -12,6 +12,7 @@ M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v M_DEPS += ../../../library/common/ad_edge_detect.v

9
projects/cn0561/coraz7s/system_bd.tcl
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@ -23,13 +23,4 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_I2C0_IO EMIO
ad_connect iic_0_io sys_ps7/IIC_0 ad_connect iic_0_io sys_ps7/IIC_0
# specify ADC resolution -- the design supports 16/24/32 bit resolutions
set adc_resolution 24
# ADC number of channels
set adc_num_of_channels 4
source ../common/cn0561_bd.tcl source ../common/cn0561_bd.tcl

2
projects/cn0561/zed/Makefile
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@ -11,9 +11,9 @@ M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v M_DEPS += ../../../library/common/ad_edge_detect.v
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
LIB_DEPS += axi_clkgen LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac

8
projects/cn0561/zed/system_bd.tcl
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@ -15,12 +15,4 @@ adi_project_files cn0561_fmc_zed [list \
sysid_gen_sys_init_file sysid_gen_sys_init_file
# specify ADC resolution -- the design supports 16/24/32 bit resolutions
set adc_resolution 24
# ADC number of channels
set adc_num_of_channels 4
source ../common/cn0561_bd.tcl source ../common/cn0561_bd.tcl

1
projects/cn0561/zed/system_constr.xdc
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@ -1,4 +1,3 @@
# cn0561 SPI configuration interface # cn0561 SPI configuration interface
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sdi] ; ## FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports cn0561_spi_sdi] ; ## FMC_LPC_LA03_P

1
projects/cn0561/zed/system_project.tcl
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@ -11,4 +11,3 @@ adi_project_files cn0561_zed [list \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run cn0561_zed adi_project_run cn0561_zed

1
projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl
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@ -1,4 +1,3 @@
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 pulsar_adc_spi create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 pulsar_adc_spi
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl

1
projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl
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@ -10,4 +10,3 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path";
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file sysid_gen_sys_init_file

2
projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc
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@ -1,4 +1,3 @@
# ad40xx_fmc SPI interface # ad40xx_fmc SPI interface
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo] ; ## PMOD JA [2] set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo] ; ## PMOD JA [2]
@ -17,4 +16,3 @@ set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/spi_pulsar_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]

1
projects/pulsar_adc_pmdz/coraz7s/system_project.tcl
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@ -11,4 +11,3 @@ adi_project_files pulsar_adc_pmdz_coraz7s [list \
"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"] "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
adi_project_run pulsar_adc_pmdz_coraz7s adi_project_run pulsar_adc_pmdz_coraz7s