ad_dcfilter: Fix filter loopback
Istvan Csomortani
parent
a54e4edb08
commit
2b15c7313e
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@ -1,193 +1,192 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
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`timescale 1ps/1ps
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module ad_dcfilter (
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// data interface
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clk,
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valid,
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data,
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valid_out,
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data_out,
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// control interface
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dcfilt_enb,
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dcfilt_coeff,
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dcfilt_offset);
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// data interface
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input clk;
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input valid;
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input [15:0] data;
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output valid_out;
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output [15:0] data_out;
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// control interface
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input dcfilt_enb;
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input [15:0] dcfilt_coeff;
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input [15:0] dcfilt_offset;
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// internal registers
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reg [15:0] dc_offset = 'd0;
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reg [15:0] dc_offset_d = 'd0;
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reg valid_d = 'd0;
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reg [15:0] data_d = 'd0;
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reg valid_2d = 'd0;
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reg [15:0] data_2d = 'd0;
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reg [15:0] data_dcfilt = 'd0;
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reg valid_out = 'd0;
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reg [15:0] data_out = 'd0;
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// internal signals
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wire [14:0] dc_offset_15_s;
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wire [32:0] dc_offset_33_s;
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// cancelling the dc offset
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always @(posedge clk) begin
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dc_offset <= dc_offset_33_s[32:17];
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dc_offset_d <= dc_offset;
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valid_d <= valid;
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if (valid == 1'b1) begin
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data_d <= data + dcfilt_offset;
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end
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valid_2d <= valid_d;
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data_2d <= data_d;
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data_dcfilt <= data_d - dc_offset;
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if (dcfilt_enb == 1'b1) begin
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valid_out <= valid_2d;
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data_out <= data_dcfilt;
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end else begin
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valid_out <= valid_2d;
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data_out <= data_2d;
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end
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end
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// dsp slice instance ((D-A)*B)+C
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DSP48E1 #(
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.ACASCREG (1),
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.ADREG (1),
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.ALUMODEREG (0),
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.AREG (1),
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.AUTORESET_PATDET ("NO_RESET"),
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.A_INPUT ("DIRECT"),
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.BCASCREG (1),
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.BREG (1),
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.B_INPUT ("DIRECT"),
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.CARRYINREG (0),
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.CARRYINSELREG (0),
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.CREG (1),
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.DREG (0),
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.INMODEREG (0),
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.MASK (48'h3fffffffffff),
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.MREG (1),
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.OPMODEREG (0),
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.PATTERN (48'h000000000000),
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.PREG (0),
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.SEL_MASK ("MASK"),
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.SEL_PATTERN ("PATTERN"),
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.USE_DPORT ("TRUE"),
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.USE_MULT ("MULTIPLY"),
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.USE_PATTERN_DETECT ("NO_PATDET"),
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.USE_SIMD ("ONE48"))
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i_dsp48e1 (
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.CLK (clk),
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.A ({{14{dc_offset_33_s[32]}}, dc_offset_33_s[32:17]}),
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.B ({{2{dcfilt_coeff[15]}}, dcfilt_coeff}),
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.C ({{32{dc_offset_d[15]}}, dc_offset_d}),
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.D ({{9{data_d[15]}}, data_d}),
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.MULTSIGNIN (1'd0),
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.CARRYIN (1'd0),
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.CARRYCASCIN (1'd0),
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.ACIN (30'd0),
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.BCIN (18'd0),
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.PCIN (48'd0),
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.P ({dc_offset_15_s, dc_offset_33_s}),
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.MULTSIGNOUT (),
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.CARRYOUT (),
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.CARRYCASCOUT (),
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.ACOUT (),
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.BCOUT (),
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.PCOUT (),
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.ALUMODE (4'd0),
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.CARRYINSEL (3'd0),
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.INMODE (5'b01100),
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.OPMODE (7'b0110101),
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.PATTERNBDETECT (),
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.PATTERNDETECT (),
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.OVERFLOW (),
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.UNDERFLOW (),
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.CEA1 (1'd0),
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.CEA2 (1'd1),
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.CEAD (1'd1),
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.CEALUMODE (1'd0),
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.CEB1 (1'd0),
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.CEB2 (1'd1),
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.CEC (1'd1),
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.CECARRYIN (1'd0),
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.CECTRL (1'd0),
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.CED (1'd1),
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.CEINMODE (1'd0),
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.CEM (1'd1),
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.CEP (1'd0),
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.RSTA (1'd0),
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.RSTALLCARRYIN (1'd0),
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.RSTALUMODE (1'd0),
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.RSTB (1'd0),
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.RSTC (1'd0),
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.RSTCTRL (1'd0),
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.RSTD (1'd0),
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.RSTINMODE (1'd0),
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.RSTM (1'd0),
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.RSTP (1'd0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
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// - Redistributions in binary form must reproduce the above copyright
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||||
// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
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||||
// from the requirement that you obtain separate licenses from these
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||||
// patent holders to use this software.
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||||
// - Use of the software either in source or binary form, must be run
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||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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||||
//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
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`timescale 1ps/1ps
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module ad_dcfilter (
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// data interface
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clk,
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valid,
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data,
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valid_out,
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data_out,
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// control interface
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dcfilt_enb,
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dcfilt_coeff,
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dcfilt_offset);
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// data interface
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input clk;
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input valid;
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input [15:0] data;
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output valid_out;
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output [15:0] data_out;
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// control interface
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input dcfilt_enb;
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input [15:0] dcfilt_coeff;
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input [15:0] dcfilt_offset;
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// internal registers
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reg [47:0] dc_offset = 'd0;
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reg [47:0] dc_offset_d = 'd0;
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reg valid_d = 'd0;
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reg [15:0] data_d = 'd0;
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reg valid_2d = 'd0;
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reg [15:0] data_2d = 'd0;
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reg [15:0] data_dcfilt = 'd0;
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reg valid_out = 'd0;
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reg [15:0] data_out = 'd0;
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// internal signals
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wire [47:0] dc_offset_s;
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// cancelling the dc offset
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always @(posedge clk) begin
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dc_offset <= dc_offset_s;
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dc_offset_d <= dc_offset;
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valid_d <= valid;
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if (valid == 1'b1) begin
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data_d <= data + dcfilt_offset;
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end
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valid_2d <= valid_d;
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data_2d <= data_d;
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data_dcfilt <= data_d - dc_offset[32:17];
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if (dcfilt_enb == 1'b1) begin
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valid_out <= valid_2d;
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data_out <= data_dcfilt;
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end else begin
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valid_out <= valid_2d;
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data_out <= data_2d;
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end
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end
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// dsp slice instance ((D-A)*B)+C
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DSP48E1 #(
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.ACASCREG (1),
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.ADREG (1),
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.ALUMODEREG (0),
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.AREG (1),
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.AUTORESET_PATDET ("NO_RESET"),
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.A_INPUT ("DIRECT"),
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.BCASCREG (1),
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.BREG (1),
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.B_INPUT ("DIRECT"),
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.CARRYINREG (0),
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.CARRYINSELREG (0),
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.CREG (1),
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.DREG (0),
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.INMODEREG (0),
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.MASK (48'h3fffffffffff),
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.MREG (1),
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.OPMODEREG (0),
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.PATTERN (48'h000000000000),
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.PREG (0),
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.SEL_MASK ("MASK"),
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.SEL_PATTERN ("PATTERN"),
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.USE_DPORT ("TRUE"),
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.USE_MULT ("MULTIPLY"),
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.USE_PATTERN_DETECT ("NO_PATDET"),
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.USE_SIMD ("ONE48"))
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i_dsp48e1 (
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.CLK (clk),
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.A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}),
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.B ({{2{dcfilt_coeff[15]}}, dcfilt_coeff}),
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.C (dc_offset_d),
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.D ({{9{data_d[15]}}, data_d}),
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.MULTSIGNIN (1'd0),
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.CARRYIN (1'd0),
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.CARRYCASCIN (1'd0),
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.ACIN (30'd0),
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.BCIN (18'd0),
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.PCIN (48'd0),
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.P (dc_offset_s),
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.MULTSIGNOUT (),
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.CARRYOUT (),
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.CARRYCASCOUT (),
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.ACOUT (),
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.BCOUT (),
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.PCOUT (),
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.ALUMODE (4'd0),
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.CARRYINSEL (3'd0),
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.INMODE (5'b01100),
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.OPMODE (7'b0110101),
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.PATTERNBDETECT (),
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.PATTERNDETECT (),
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.OVERFLOW (),
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.UNDERFLOW (),
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.CEA1 (1'd0),
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.CEA2 (1'd1),
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.CEAD (1'd1),
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.CEALUMODE (1'd0),
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.CEB1 (1'd0),
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.CEB2 (1'd1),
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.CEC (1'd1),
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.CECARRYIN (1'd0),
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.CECTRL (1'd0),
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.CED (1'd1),
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.CEINMODE (1'd0),
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.CEM (1'd1),
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.CEP (1'd0),
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.RSTA (1'd0),
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.RSTALLCARRYIN (1'd0),
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.RSTALUMODE (1'd0),
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.RSTB (1'd0),
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.RSTC (1'd0),
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.RSTCTRL (1'd0),
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.RSTD (1'd0),
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.RSTINMODE (1'd0),
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.RSTM (1'd0),
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.RSTP (1'd0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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