axi_dmac: Fix some indentation errors
Purely cosmetic. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
parent
8b8d346193
commit
2b2c1f6a1e
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@ -52,7 +52,7 @@ module dmac_address_generator #(
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output reg [ID_WIDTH-1:0] id,
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input [ID_WIDTH-1:0] request_id,
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input sync_id,
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input sync_id,
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input eot,
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@ -60,14 +60,14 @@ module dmac_address_generator #(
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input pause,
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output reg enabled,
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input addr_ready,
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output reg addr_valid,
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input addr_ready,
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output reg addr_valid,
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output [DMA_ADDR_WIDTH-1:0] addr,
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output [LENGTH_WIDTH-1:0] len,
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output [ 2:0] size,
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output [ 1:0] burst,
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output [ 2:0] prot,
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output [ 3:0] cache
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output [LENGTH_WIDTH-1:0] len,
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output [ 2:0] size,
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output [ 1:0] burst,
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output [ 2:0] prot,
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output [ 3:0] cache
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);
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localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}};
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@ -89,7 +89,7 @@ module axi_dmac #(
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// Write address
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output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_awaddr,
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output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
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output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
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output [ 2:0] m_dest_axi_awsize,
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output [ 1:0] m_dest_axi_awburst,
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output [ 2:0] m_dest_axi_awprot,
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@ -98,8 +98,8 @@ module axi_dmac #(
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input m_dest_axi_awready,
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// Write data
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output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
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output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
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output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
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output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
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input m_dest_axi_wready,
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output m_dest_axi_wvalid,
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output m_dest_axi_wlast,
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@ -112,7 +112,7 @@ module axi_dmac #(
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// Unused read interface
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output m_dest_axi_arvalid,
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output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_araddr,
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output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
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output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
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output [ 2:0] m_dest_axi_arsize,
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output [ 1:0] m_dest_axi_arburst,
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output [ 3:0] m_dest_axi_arcache,
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@ -120,7 +120,7 @@ module axi_dmac #(
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input m_dest_axi_arready,
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input m_dest_axi_rvalid,
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input [ 1:0] m_dest_axi_rresp,
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input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
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input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
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output m_dest_axi_rready,
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// Master AXI interface
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@ -131,14 +131,14 @@ module axi_dmac #(
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input m_src_axi_arready,
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output m_src_axi_arvalid,
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output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_araddr,
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output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
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output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
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output [ 2:0] m_src_axi_arsize,
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output [ 1:0] m_src_axi_arburst,
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output [ 2:0] m_src_axi_arprot,
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output [ 3:0] m_src_axi_arcache,
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// Read data and response
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input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
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input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
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output m_src_axi_rready,
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input m_src_axi_rvalid,
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input [ 1:0] m_src_axi_rresp,
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@ -146,15 +146,15 @@ module axi_dmac #(
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// Unused write interface
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output m_src_axi_awvalid,
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output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_awaddr,
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output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
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output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
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output [ 2:0] m_src_axi_awsize,
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output [ 1:0] m_src_axi_awburst,
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output [ 3:0] m_src_axi_awcache,
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output [ 2:0] m_src_axi_awprot,
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input m_src_axi_awready,
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output m_src_axi_wvalid,
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output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
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output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
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output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
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output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
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output m_src_axi_wlast,
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input m_src_axi_wready,
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input m_src_axi_bvalid,
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@ -165,7 +165,7 @@ module axi_dmac #(
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input s_axis_aclk,
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output s_axis_ready,
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input s_axis_valid,
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input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
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input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
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input [0:0] s_axis_user,
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input s_axis_last,
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output s_axis_xfer_req,
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@ -174,14 +174,14 @@ module axi_dmac #(
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input m_axis_aclk,
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input m_axis_ready,
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output m_axis_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
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output m_axis_last,
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output m_axis_xfer_req,
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output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
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output m_axis_last,
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output m_axis_xfer_req,
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// Input FIFO interface
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input fifo_wr_clk,
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input fifo_wr_en,
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input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
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input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
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output fifo_wr_overflow,
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input fifo_wr_sync,
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output fifo_wr_xfer_req,
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@ -190,9 +190,9 @@ module axi_dmac #(
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input fifo_rd_clk,
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input fifo_rd_en,
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output fifo_rd_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
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output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
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output fifo_rd_underflow,
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output fifo_rd_xfer_req
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output fifo_rd_xfer_req
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);
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@ -394,10 +394,10 @@ begin
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9'h002: up_scratch <= up_wdata;
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9'h020: up_irq_mask <= up_wdata[1:0];
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9'h100: {up_pause, up_enable} <= up_wdata[1:0];
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9'h103: begin
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if (CYCLIC) up_dma_cyclic <= up_wdata[0];
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up_axis_xlast <= up_wdata[1];
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end
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9'h103: begin
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if (CYCLIC) up_dma_cyclic <= up_wdata[0];
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up_axis_xlast <= up_wdata[1];
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end
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9'h104: up_dma_dest_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
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9'h105: up_dma_src_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
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9'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
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@ -601,18 +601,16 @@ dmac_request_arb #(
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.req_dest_address(dma_req_dest_address),
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.req_src_address(dma_req_src_address),
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.req_length(dma_req_length),
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.req_xlast(up_axis_xlast),
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.req_xlast(up_axis_xlast),
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.req_sync_transfer_start(dma_req_sync_transfer_start),
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.eot(dma_req_eot),
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.m_dest_axi_aclk(m_dest_axi_aclk),
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.m_dest_axi_aresetn(m_dest_axi_aresetn),
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.m_src_axi_aclk(m_src_axi_aclk),
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.m_src_axi_aresetn(m_src_axi_aresetn),
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.m_axi_awaddr(m_dest_axi_awaddr),
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.m_axi_awlen(m_dest_axi_awlen),
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.m_axi_awsize(m_dest_axi_awsize),
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@ -622,19 +620,16 @@ dmac_request_arb #(
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.m_axi_awvalid(m_dest_axi_awvalid),
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.m_axi_awready(m_dest_axi_awready),
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.m_axi_wdata(m_dest_axi_wdata),
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.m_axi_wstrb(m_dest_axi_wstrb),
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.m_axi_wready(m_dest_axi_wready),
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.m_axi_wvalid(m_dest_axi_wvalid),
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.m_axi_wlast(m_dest_axi_wlast),
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.m_axi_bvalid(m_dest_axi_bvalid),
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.m_axi_bresp(m_dest_axi_bresp),
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.m_axi_bready(m_dest_axi_bready),
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.m_axi_arready(m_src_axi_arready),
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.m_axi_arvalid(m_src_axi_arvalid),
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.m_axi_araddr(m_src_axi_araddr),
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@ -644,13 +639,11 @@ dmac_request_arb #(
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.m_axi_arprot(m_src_axi_arprot),
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.m_axi_arcache(m_src_axi_arcache),
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.m_axi_rdata(m_src_axi_rdata),
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.m_axi_rready(m_src_axi_rready),
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.m_axi_rvalid(m_src_axi_rvalid),
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.m_axi_rresp(m_src_axi_rresp),
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.s_axis_aclk(s_axis_aclk),
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.s_axis_ready(s_axis_ready),
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.s_axis_valid(s_axis_valid),
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@ -659,14 +652,12 @@ dmac_request_arb #(
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.s_axis_last(s_axis_last),
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.s_axis_xfer_req(s_axis_xfer_req),
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.m_axis_aclk(m_axis_aclk),
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.m_axis_ready(m_axis_ready),
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.m_axis_valid(m_axis_valid),
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.m_axis_data(m_axis_data),
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.m_axis_last(m_axis_last),
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.m_axis_xfer_req(m_axis_xfer_req),
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.m_axis_last(m_axis_last),
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.m_axis_xfer_req(m_axis_xfer_req),
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.fifo_wr_clk(fifo_wr_clk),
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.fifo_wr_en(fifo_wr_en),
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@ -675,13 +666,12 @@ dmac_request_arb #(
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.fifo_wr_sync(fifo_wr_sync),
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.fifo_wr_xfer_req(fifo_wr_xfer_req),
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.fifo_rd_clk(fifo_rd_clk),
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.fifo_rd_en(fifo_rd_en),
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.fifo_rd_valid(fifo_rd_valid),
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.fifo_rd_dout(fifo_rd_dout),
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.fifo_rd_underflow(fifo_rd_underflow),
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.fifo_rd_xfer_req(fifo_rd_xfer_req),
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.fifo_rd_xfer_req(fifo_rd_xfer_req),
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// DBG
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.dbg_dest_request_id(dest_request_id),
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@ -46,7 +46,7 @@ module dmac_dest_axi_stream #(
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output enabled,
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input sync_id,
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output sync_id_ret,
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output xfer_req,
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output xfer_req,
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input [ID_WIDTH-1:0] request_id,
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output [ID_WIDTH-1:0] response_id,
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@ -57,7 +57,7 @@ module dmac_dest_axi_stream #(
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input m_axis_ready,
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output m_axis_valid,
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output [S_AXIS_DATA_WIDTH-1:0] m_axis_data,
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output m_axis_last,
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output m_axis_last,
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output fifo_ready,
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input fifo_valid,
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@ -66,7 +66,7 @@ module dmac_dest_axi_stream #(
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input req_valid,
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output req_ready,
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input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
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input req_xlast,
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input req_xlast,
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output response_valid,
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input response_ready,
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@ -108,7 +108,7 @@ dmac_data_mover # (
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.enable(enable),
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.enabled(data_enabled),
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.sync_id(sync_id),
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.xfer_req(xfer_req),
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.xfer_req(xfer_req),
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.request_id(request_id),
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.response_id(data_id),
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@ -121,7 +121,7 @@ dmac_data_mover # (
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.m_axi_ready(m_axis_ready),
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.m_axi_valid(m_axis_valid),
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.m_axi_data(m_axis_data),
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.m_axi_last(m_axis_last_s),
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.m_axi_last(m_axis_last_s),
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.s_axi_ready(_fifo_ready),
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.s_axi_valid(fifo_valid),
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.s_axi_data(fifo_data)
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@ -98,7 +98,7 @@ dmac_data_mover # (
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.enable(enable),
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.enabled(data_enabled),
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.sync_id(sync_id),
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.xfer_req(xfer_req),
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.xfer_req(xfer_req),
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.request_id(request_id),
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.response_id(data_id),
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@ -61,7 +61,7 @@ module dmac_request_arb #(
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input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
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input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
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input [DMA_LENGTH_WIDTH-1:0] req_length,
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input req_xlast,
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input req_xlast,
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input req_sync_transfer_start,
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output reg eot,
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@ -88,9 +88,9 @@ module dmac_request_arb #(
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// Write data
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output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata,
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output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb,
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input m_axi_wready,
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output m_axi_wvalid,
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output m_axi_wlast,
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input m_axi_wready,
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output m_axi_wvalid,
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output m_axi_wlast,
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// Write response
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input m_axi_bvalid,
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@ -108,7 +108,7 @@ module dmac_request_arb #(
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output [ 3:0] m_axi_arcache,
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// Read data and response
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input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata,
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input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata,
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output m_axi_rready,
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input m_axi_rvalid,
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input [ 1:0] m_axi_rresp,
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@ -117,7 +117,7 @@ module dmac_request_arb #(
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input s_axis_aclk,
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output s_axis_ready,
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input s_axis_valid,
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input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
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input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
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input s_axis_last,
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input [0:0] s_axis_user,
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output s_axis_xfer_req,
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@ -126,14 +126,14 @@ module dmac_request_arb #(
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input m_axis_aclk,
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input m_axis_ready,
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output m_axis_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
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output m_axis_last,
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output m_axis_xfer_req,
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output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
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output m_axis_last,
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output m_axis_xfer_req,
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// Input FIFO interface
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input fifo_wr_clk,
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input fifo_wr_en,
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input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
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input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
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output fifo_wr_overflow,
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input fifo_wr_sync,
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output fifo_wr_xfer_req,
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@ -142,18 +142,18 @@ module dmac_request_arb #(
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input fifo_rd_clk,
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input fifo_rd_en,
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output fifo_rd_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
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output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
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output fifo_rd_underflow,
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output fifo_rd_xfer_req,
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output fifo_rd_xfer_req,
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output [ID_WIDTH-1:0] dbg_dest_request_id,
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output [ID_WIDTH-1:0] dbg_dest_address_id,
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output [ID_WIDTH-1:0] dbg_dest_data_id,
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output [ID_WIDTH-1:0] dbg_dest_response_id,
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output [ID_WIDTH-1:0] dbg_src_request_id,
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output [ID_WIDTH-1:0] dbg_src_address_id,
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output [ID_WIDTH-1:0] dbg_src_data_id,
|
||||
output [ID_WIDTH-1:0] dbg_src_response_id,
|
||||
output [ID_WIDTH-1:0] dbg_dest_request_id,
|
||||
output [ID_WIDTH-1:0] dbg_dest_address_id,
|
||||
output [ID_WIDTH-1:0] dbg_dest_data_id,
|
||||
output [ID_WIDTH-1:0] dbg_dest_response_id,
|
||||
output [ID_WIDTH-1:0] dbg_src_request_id,
|
||||
output [ID_WIDTH-1:0] dbg_src_address_id,
|
||||
output [ID_WIDTH-1:0] dbg_src_data_id,
|
||||
output [ID_WIDTH-1:0] dbg_src_response_id,
|
||||
output [7:0] dbg_status
|
||||
);
|
||||
|
||||
|
@ -503,7 +503,7 @@ dmac_dest_axi_stream #(
|
|||
.req_valid(dest_req_valid),
|
||||
.req_ready(dest_req_ready),
|
||||
.req_last_burst_length(dest_req_last_burst_length),
|
||||
.req_xlast(dest_req_xlast),
|
||||
.req_xlast(dest_req_xlast),
|
||||
|
||||
.response_valid(dest_response_valid),
|
||||
.response_ready(dest_response_ready),
|
||||
|
@ -515,7 +515,7 @@ dmac_dest_axi_stream #(
|
|||
.data_id(data_id),
|
||||
.sync_id(dest_sync_id),
|
||||
.sync_id_ret(dest_sync_id_ret),
|
||||
.xfer_req(m_axis_xfer_req),
|
||||
.xfer_req(m_axis_xfer_req),
|
||||
|
||||
.data_eot(data_eot),
|
||||
.response_eot(response_eot),
|
||||
|
@ -527,7 +527,7 @@ dmac_dest_axi_stream #(
|
|||
.m_axis_valid(m_axis_valid),
|
||||
.m_axis_ready(m_axis_ready),
|
||||
.m_axis_data(m_axis_data),
|
||||
.m_axis_last(m_axis_last)
|
||||
.m_axis_last(m_axis_last)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
@ -588,7 +588,7 @@ dmac_dest_fifo_inf #(
|
|||
.valid(fifo_rd_valid),
|
||||
.dout(fifo_rd_dout),
|
||||
.underflow(fifo_rd_underflow),
|
||||
.xfer_req(fifo_rd_xfer_req)
|
||||
.xfer_req(fifo_rd_xfer_req)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
|
Loading…
Reference in New Issue