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axi_dmac: Align the data_ready to data 

The commit 6900c have added an additional register stage into the fifo read
data path, but the control signals (ready/valid/underflow) were not realigned
to the data. This can cause data lose or duplicated samples in some case.
Realign the control signals to the data.
main
Istvan Csomortani 2017-11-21 12:59:40 +00:00
parent ec324652aa
commit 2b2c6b57f9
1 changed files with 10 additions and 16 deletions
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26
library/axi_dmac/dest_fifo_inf.v
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@ -55,8 +55,8 @@ module dmac_dest_fifo_inf #(
input en,
output reg [DATA_WIDTH-1:0] dout,
output valid,
output underflow,
output reg valid,
output reg underflow,
output xfer_req,
@ -81,22 +81,10 @@ wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
wire [DATA_WIDTH-1:0] dout_s;
reg en_d1;
wire data_ready;
wire data_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
en_d1 <= 1'b0;
end else begin
en_d1 <= en;
end
end
assign underflow = en_d1 & (~data_valid | ~enable);
assign data_ready = en_d1 & (data_valid | ~enable);
assign valid = en_d1 & data_valid & enable;
assign data_ready = en & (data_valid | ~enable);
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
@ -130,8 +118,14 @@ dmac_data_mover # (
);
always @(posedge clk) begin
if (en)
if (en) begin
dout <= (data_valid) ? dout_s : {DATA_WIDTH{1'b0}};
valid <= data_valid & enable;
underflow <= ~(data_valid & enable);
end else begin
valid <= 1'b0;
underflow <= 1'b0;
end
end
dmac_response_generator # (