data_offload: Fix duplicated output samples
Signed-off-by: David Winter <david.winter@analog.com>main
parent
04f2d19d4b
commit
2b55c7453b
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@ -64,7 +64,7 @@ module data_offload_fsm #(
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input rd_ready,
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output reg rd_valid = 1'b0,
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output reg [RD_ADDRESS_WIDTH-1:0] rd_addr,
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output reg rd_last,
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output rd_last,
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output reg [RD_DATA_WIDTH/8-1:0] rd_tkeep,
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input rd_oneshot, // 0 - CYCLIC; 1 - ONE_SHOT;
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@ -375,18 +375,12 @@ module data_offload_fsm #(
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end
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assign rd_empty_s = (rd_addr == rd_last_addr) ? 1'b1 : 1'b0;
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assign rd_last = rd_oneshot & rd_empty_s;
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always @(posedge rd_clk) begin
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if (rd_resetn_in == 1'b0) begin
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rd_last <= 1'b0;
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rd_isempty <= 1'b0;
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end else begin
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rd_isempty <= rd_empty_s;
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if (rd_empty_s & ~rd_isempty) begin
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// in CYCLIC mode rd_last stays low
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rd_last <= rd_oneshot;
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end else if (rd_last & rd_ready & rd_valid)begin
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rd_last <= 1'b0;
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end
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end
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end
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@ -394,7 +388,7 @@ module data_offload_fsm #(
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if (rd_resetn_in == 1'b0) begin
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rd_valid <= 1'b0;
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end else begin
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if ((rd_ready) && (rd_fsm_state == RD_READ_FROM_MEM)) begin
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if ((rd_ready) && (rd_fsm_state == RD_READ_FROM_MEM) && !(rd_valid && rd_last && rd_oneshot)) begin
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rd_valid <= 1'b1;
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end else begin
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rd_valid <= 1'b0;
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