From 2b84fbb3b321767071d0727db10bd2b51baadcfb Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 4 Aug 2017 13:17:23 +0200 Subject: [PATCH] jesd204: Use consistent naming scheme for CDC blocks Name all CDC blocks following the patter i_cdc_${signal_name}. This makes it clear what is going on. Signed-off-by: Lars-Peter Clausen --- .../axi_jesd204_common/jesd204_up_sysref.v | 2 +- .../axi_jesd204_rx/axi_jesd204_rx_constr.xdc | 28 +++++++-------- .../axi_jesd204_rx/jesd204_up_ilas_mem.v | 2 +- .../jesd204/axi_jesd204_rx/jesd204_up_rx.v | 2 +- .../axi_jesd204_rx/jesd204_up_rx_lane.v | 2 +- .../axi_jesd204_tx/axi_jesd204_tx_constr.xdc | 34 +++++++++---------- .../jesd204/axi_jesd204_tx/jesd204_up_tx.v | 6 ++-- library/jesd204/jesd204_tx/tx_ctrl.v | 2 +- 8 files changed, 39 insertions(+), 39 deletions(-) diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v index af7d219db..dc2ea2767 100644 --- a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v +++ b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v @@ -71,7 +71,7 @@ wire [1:0] up_sysref_event; sync_event #( .NUM_OF_EVENTS(2) -) i_sysref_event_sync ( +) i_cdc_sysref_event ( .in_clk(core_clk), .in_event({ core_event_sysref_alignment_error, diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc index 9174a6c8b..911b28ce8 100644 --- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc @@ -56,34 +56,34 @@ set_property ASYNC_REG TRUE \ [get_cells -hier {up_reset_synchronizer_vector_reg*}] set_false_path \ - -from [get_pins {i_up_rx/i_sync_status/in_toggle_d1_reg/C}] \ - -to [get_pins {i_up_rx/i_sync_status/i_sync_out/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_rx/i_cdc_status/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_rx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_rx/i_sync_status/out_toggle_d1_reg/C}] \ - -to [get_pins {i_up_rx/i_sync_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_rx/i_cdc_status/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_rx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_sysref/i_sysref_event_sync/in_toggle_d1_reg/C}] \ - -to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_sysref/i_sysref_event_sync/out_toggle_d1_reg/C}] \ - -to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_sysref/i_sysref_event_sync/cdc_hold_reg*/C}] \ - -to [get_pins {i_up_sysref/i_sysref_event_sync/out_event_reg*/D}] + -from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}] # Don't place them too far appart set_max_delay -datapath_only \ - -from [get_pins {i_up_rx/i_sync_status/cdc_hold_reg[*]/C}] \ - -to [get_pins {i_up_rx/i_sync_status/out_data_reg[*]/D}] \ + -from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \ + -to [get_pins {i_up_rx/i_cdc_status/out_data_reg[*]/D}] \ [get_property -min PERIOD $axi_clk] set_false_path \ -from $core_clk \ - -to [get_pins {i_up_rx/*i_up_rx_lane/i_sync_status_ready/cdc_sync_stage1_reg*/D}] + -to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}] set_max_delay -datapath_only \ -from $core_clk \ @@ -92,7 +92,7 @@ set_max_delay -datapath_only \ set_false_path \ -from $core_clk \ - -to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_sync_ilas_ready/cdc_sync_stage1_reg[0]/D}] + -to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_cdc_ilas_ready/cdc_sync_stage1_reg[0]/D}] set_max_delay -datapath_only \ -from [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/*mem_reg*/CLK}] \ diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v index a48f2ff12..4fee49b56 100644 --- a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v @@ -61,7 +61,7 @@ module jesd204_up_ilas_mem ( reg [3:0] mem[0:31]; reg core_ilas_captured = 1'b0; -sync_bits i_sync_ilas_ready ( +sync_bits i_cdc_ilas_ready ( .in(core_ilas_captured), .out_resetn(1'b1), .out_clk(up_clk), diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v index 1cfe2eb88..b4312e162 100644 --- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v @@ -80,7 +80,7 @@ wire [31:0] up_lane_rdata[0:NUM_LANES-1]; sync_data #( .NUM_OF_BITS(3+NUM_LANES*(2)) -) i_sync_status ( +) i_cdc_status ( .in_clk(core_clk), .in_data({ core_status_ctrl_state, diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v index 7348cc805..16a3cd900 100644 --- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v @@ -72,7 +72,7 @@ wire up_ilas_ready; sync_bits #( .NUM_OF_BITS(1) -) i_sync_status_ready ( +) i_cdc_status_ready ( .in({ core_status_ifs_ready }), diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc index dcb9ba9f8..08de67646 100644 --- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc @@ -56,34 +56,34 @@ set_property ASYNC_REG TRUE \ [get_cells -hier {up_reset_synchronizer_vector_reg*}] set_false_path \ - -from [get_pins {i_up_tx/i_sync_state/out_toggle_d1_reg/C}] \ - -to [get_pins {i_up_tx/i_sync_state/i_sync_in/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_tx/i_cdc_status/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_tx/i_sync_state/in_toggle_d1_reg/C}] \ - -to [get_pins {i_up_tx/i_sync_state/i_sync_out/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_tx/i_cdc_status/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_sysref/i_sysref_event_sync/in_toggle_d1_reg/C}] \ - -to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_sysref/i_sysref_event_sync/out_toggle_d1_reg/C}] \ - -to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_sysref/i_sysref_event_sync/cdc_hold_reg*/C}] \ - -to [get_pins {i_up_sysref/i_sysref_event_sync/out_event_reg*/D}] + -from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}] # Don't place them too far appart set_max_delay -datapath_only \ - -from [get_pins {i_up_tx/i_sync_state/cdc_hold_reg[*]/C}] \ - -to [get_pins {i_up_tx/i_sync_state/out_data_reg[*]/D}] \ + -from [get_pins {i_up_tx/i_cdc_status/cdc_hold_reg[*]/C}] \ + -to [get_pins {i_up_tx/i_cdc_status/out_data_reg[*]/D}] \ [get_property -min PERIOD $axi_clk] set_false_path \ -from $core_clk \ - -to [get_pins {i_up_tx/i_sync_sync/cdc_sync_stage1_reg[0]/D}] + -to [get_pins {i_up_tx/i_cdc_sync/cdc_sync_stage1_reg[0]/D}] set_false_path \ -from [get_pins {i_up_common/up_reset_core_reg/C}] \ @@ -114,9 +114,9 @@ set_max_delay -datapath_only \ [get_property -min PERIOD $core_clk] set_false_path \ - -from [get_pins {i_up_tx/i_sync_manual_sync_request/out_toggle_d1_reg/C}] \ - -to [get_pins {i_up_tx/i_sync_manual_sync_request/i_sync_in/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_tx/i_cdc_manual_sync_request/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_in/cdc_sync_stage1_reg[0]/D}] set_false_path \ - -from [get_pins {i_up_tx/i_sync_manual_sync_request/in_toggle_d1_reg/C}] \ - -to [get_pins {i_up_tx/i_sync_manual_sync_request/i_sync_out/cdc_sync_stage1_reg[0]/D}] + -from [get_pins {i_up_tx/i_cdc_manual_sync_request/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_out/cdc_sync_stage1_reg[0]/D}] diff --git a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v index d9dc223e9..7efa63ba6 100644 --- a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v +++ b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v @@ -78,7 +78,7 @@ reg up_ctrl_manual_sync_request = 1'b0; wire [1:0] up_status_state; wire up_status_sync; -sync_bits i_sync_sync ( +sync_bits i_cdc_sync ( .in(core_status_sync), .out_clk(up_clk), .out_resetn(1'b1), @@ -87,7 +87,7 @@ sync_bits i_sync_sync ( sync_data #( .NUM_OF_BITS(2) -) i_sync_state ( +) i_cdc_status ( .in_clk(core_clk), .in_data(core_status_state), .out_clk(up_clk), @@ -97,7 +97,7 @@ sync_data #( sync_event #( .NUM_OF_EVENTS(1), .ASYNC_CLK(1) -) i_sync_manual_sync_request ( +) i_cdc_manual_sync_request ( .in_clk(up_clk), .in_event(up_ctrl_manual_sync_request), .out_clk(core_clk), diff --git a/library/jesd204/jesd204_tx/tx_ctrl.v b/library/jesd204/jesd204_tx/tx_ctrl.v index 08d9f0f2e..1eaa3d02e 100644 --- a/library/jesd204/jesd204_tx/tx_ctrl.v +++ b/library/jesd204/jesd204_tx/tx_ctrl.v @@ -89,7 +89,7 @@ reg ilas_config_rd_d1 = 1'b1; reg last_ilas_mframe = 1'b0; reg cgs_enable = 1'b1; -sync_bits i_sync_sync ( +sync_bits i_cdc_sync ( .in(sync), .out_clk(clk), .out_resetn(1'b1),