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jesd204: Use consistent naming scheme for CDC blocks 

Name all CDC blocks following the patter i_cdc_${signal_name}. This makes
it clear what is going on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-08-04 13:17:23 +02:00
parent 918f226f3b
commit 2b84fbb3b3
8 changed files with 39 additions and 39 deletions
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2
library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
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@ -71,7 +71,7 @@ wire [1:0] up_sysref_event;
sync_event #( sync_event #(
.NUM_OF_EVENTS(2) .NUM_OF_EVENTS(2)
) i_sysref_event_sync ( ) i_cdc_sysref_event (
.in_clk(core_clk), .in_clk(core_clk),
.in_event({ .in_event({
core_event_sysref_alignment_error, core_event_sysref_alignment_error,

28
library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
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@ -56,34 +56,34 @@ set_property ASYNC_REG TRUE \
[get_cells -hier {up_reset_synchronizer_vector_reg*}] [get_cells -hier {up_reset_synchronizer_vector_reg*}]
set_false_path \ set_false_path \
-from [get_pins {i_up_rx/i_sync_status/in_toggle_d1_reg/C}] \ -from [get_pins {i_up_rx/i_cdc_status/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_sync_status/i_sync_out/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_rx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_rx/i_sync_status/out_toggle_d1_reg/C}] \ -from [get_pins {i_up_rx/i_cdc_status/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_sync_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_rx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_sysref/i_sysref_event_sync/in_toggle_d1_reg/C}] \ -from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_sysref/i_sysref_event_sync/out_toggle_d1_reg/C}] \ -from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_sysref/i_sysref_event_sync/cdc_hold_reg*/C}] \ -from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \
-to [get_pins {i_up_sysref/i_sysref_event_sync/out_event_reg*/D}] -to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}]
# Don't place them too far appart # Don't place them too far appart
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_pins {i_up_rx/i_sync_status/cdc_hold_reg[*]/C}] \ -from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \
-to [get_pins {i_up_rx/i_sync_status/out_data_reg[*]/D}] \ -to [get_pins {i_up_rx/i_cdc_status/out_data_reg[*]/D}] \
[get_property -min PERIOD $axi_clk] [get_property -min PERIOD $axi_clk]
set_false_path \ set_false_path \
-from $core_clk \ -from $core_clk \
-to [get_pins {i_up_rx/*i_up_rx_lane/i_sync_status_ready/cdc_sync_stage1_reg*/D}] -to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from $core_clk \ -from $core_clk \
@ -92,7 +92,7 @@ set_max_delay -datapath_only \
set_false_path \ set_false_path \
-from $core_clk \ -from $core_clk \
-to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_sync_ilas_ready/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_cdc_ilas_ready/cdc_sync_stage1_reg[0]/D}]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/*mem_reg*/CLK}] \ -from [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/*mem_reg*/CLK}] \

2
library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
View File

@ -61,7 +61,7 @@ module jesd204_up_ilas_mem (
reg [3:0] mem[0:31]; reg [3:0] mem[0:31];
reg core_ilas_captured = 1'b0; reg core_ilas_captured = 1'b0;
sync_bits i_sync_ilas_ready ( sync_bits i_cdc_ilas_ready (
.in(core_ilas_captured), .in(core_ilas_captured),
.out_resetn(1'b1), .out_resetn(1'b1),
.out_clk(up_clk), .out_clk(up_clk),

2
library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
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@ -80,7 +80,7 @@ wire [31:0] up_lane_rdata[0:NUM_LANES-1];
sync_data #( sync_data #(
.NUM_OF_BITS(3+NUM_LANES*(2)) .NUM_OF_BITS(3+NUM_LANES*(2))
) i_sync_status ( ) i_cdc_status (
.in_clk(core_clk), .in_clk(core_clk),
.in_data({ .in_data({
core_status_ctrl_state, core_status_ctrl_state,

2
library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
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@ -72,7 +72,7 @@ wire up_ilas_ready;
sync_bits #( sync_bits #(
.NUM_OF_BITS(1) .NUM_OF_BITS(1)
) i_sync_status_ready ( ) i_cdc_status_ready (
.in({ .in({
core_status_ifs_ready core_status_ifs_ready
}), }),

34
library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
View File

@ -56,34 +56,34 @@ set_property ASYNC_REG TRUE \
[get_cells -hier {up_reset_synchronizer_vector_reg*}] [get_cells -hier {up_reset_synchronizer_vector_reg*}]
set_false_path \ set_false_path \
-from [get_pins {i_up_tx/i_sync_state/out_toggle_d1_reg/C}] \ -from [get_pins {i_up_tx/i_cdc_status/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_tx/i_sync_state/i_sync_in/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_tx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_tx/i_sync_state/in_toggle_d1_reg/C}] \ -from [get_pins {i_up_tx/i_cdc_status/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_tx/i_sync_state/i_sync_out/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_tx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_sysref/i_sysref_event_sync/in_toggle_d1_reg/C}] \ -from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_sysref/i_sysref_event_sync/out_toggle_d1_reg/C}] \ -from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_sysref/i_sysref_event_sync/cdc_hold_reg*/C}] \ -from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \
-to [get_pins {i_up_sysref/i_sysref_event_sync/out_event_reg*/D}] -to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}]
# Don't place them too far appart # Don't place them too far appart
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_pins {i_up_tx/i_sync_state/cdc_hold_reg[*]/C}] \ -from [get_pins {i_up_tx/i_cdc_status/cdc_hold_reg[*]/C}] \
-to [get_pins {i_up_tx/i_sync_state/out_data_reg[*]/D}] \ -to [get_pins {i_up_tx/i_cdc_status/out_data_reg[*]/D}] \
[get_property -min PERIOD $axi_clk] [get_property -min PERIOD $axi_clk]
set_false_path \ set_false_path \
-from $core_clk \ -from $core_clk \
-to [get_pins {i_up_tx/i_sync_sync/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_tx/i_cdc_sync/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_common/up_reset_core_reg/C}] \ -from [get_pins {i_up_common/up_reset_core_reg/C}] \
@ -114,9 +114,9 @@ set_max_delay -datapath_only \
[get_property -min PERIOD $core_clk] [get_property -min PERIOD $core_clk]
set_false_path \ set_false_path \
-from [get_pins {i_up_tx/i_sync_manual_sync_request/out_toggle_d1_reg/C}] \ -from [get_pins {i_up_tx/i_cdc_manual_sync_request/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_tx/i_sync_manual_sync_request/i_sync_in/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \ set_false_path \
-from [get_pins {i_up_tx/i_sync_manual_sync_request/in_toggle_d1_reg/C}] \ -from [get_pins {i_up_tx/i_cdc_manual_sync_request/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_tx/i_sync_manual_sync_request/i_sync_out/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_out/cdc_sync_stage1_reg[0]/D}]

6
library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
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@ -78,7 +78,7 @@ reg up_ctrl_manual_sync_request = 1'b0;
wire [1:0] up_status_state; wire [1:0] up_status_state;
wire up_status_sync; wire up_status_sync;
sync_bits i_sync_sync ( sync_bits i_cdc_sync (
.in(core_status_sync), .in(core_status_sync),
.out_clk(up_clk), .out_clk(up_clk),
.out_resetn(1'b1), .out_resetn(1'b1),
@ -87,7 +87,7 @@ sync_bits i_sync_sync (
sync_data #( sync_data #(
.NUM_OF_BITS(2) .NUM_OF_BITS(2)
) i_sync_state ( ) i_cdc_status (
.in_clk(core_clk), .in_clk(core_clk),
.in_data(core_status_state), .in_data(core_status_state),
.out_clk(up_clk), .out_clk(up_clk),
@ -97,7 +97,7 @@ sync_data #(
sync_event #( sync_event #(
.NUM_OF_EVENTS(1), .NUM_OF_EVENTS(1),
.ASYNC_CLK(1) .ASYNC_CLK(1)
) i_sync_manual_sync_request ( ) i_cdc_manual_sync_request (
.in_clk(up_clk), .in_clk(up_clk),
.in_event(up_ctrl_manual_sync_request), .in_event(up_ctrl_manual_sync_request),
.out_clk(core_clk), .out_clk(core_clk),

2
library/jesd204/jesd204_tx/tx_ctrl.v
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@ -89,7 +89,7 @@ reg ilas_config_rd_d1 = 1'b1;
reg last_ilas_mframe = 1'b0; reg last_ilas_mframe = 1'b0;
reg cgs_enable = 1'b1; reg cgs_enable = 1'b1;
sync_bits i_sync_sync ( sync_bits i_cdc_sync (
.in(sync), .in(sync),
.out_clk(clk), .out_clk(clk),
.out_resetn(1'b1), .out_resetn(1'b1),