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ad_ip_jesd204_tpl_dac: expand address space to accomodate 64 channels

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Laszlo Nagy 2020-02-17 12:10:05 +00:00 committed by Laszlo Nagy
parent 59c2e581a2
commit 2ca09adaf7
3 changed files with 15 additions and 15 deletions
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8
library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
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@ -56,11 +56,11 @@ module up_tpl_common #(
input up_rstn, input up_rstn,
input up_clk, input up_clk,
input up_wreq, input up_wreq,
input [9:0] up_waddr, input [10:0] up_waddr,
input [31:0] up_wdata, input [31:0] up_wdata,
output up_wack, output up_wack,
input up_rreq, input up_rreq,
input [9:0] up_raddr, input [10:0] up_raddr,
output [31:0] up_rdata, output [31:0] up_rdata,
output up_rack output up_rack
); );
@ -77,8 +77,8 @@ module up_tpl_common #(
// decode block select // decode block select
assign up_wreq_s = (up_waddr[9:7] == {COMMON_ID,1'b1}) ? up_wreq : 1'b0; assign up_wreq_s = (up_waddr[10:7] == {COMMON_ID,1'b1}) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[9:7] == {COMMON_ID,1'b1}) ? up_rreq : 1'b0; assign up_rreq_s = (up_raddr[10:7] == {COMMON_ID,1'b1}) ? up_rreq : 1'b0;
// processor write interface // processor write interface

4
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
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@ -68,7 +68,7 @@ module ad_ip_jesd204_tpl_dac #(
input s_axi_awvalid, input s_axi_awvalid,
output s_axi_awready, output s_axi_awready,
input [11:0] s_axi_awaddr, input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot, input [2:0] s_axi_awprot,
input s_axi_wvalid, input s_axi_wvalid,
@ -82,7 +82,7 @@ module ad_ip_jesd204_tpl_dac #(
input s_axi_arvalid, input s_axi_arvalid,
output s_axi_arready, output s_axi_arready,
input [11:0] s_axi_araddr, input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot, input [2:0] s_axi_arprot,
output s_axi_rvalid, output s_axi_rvalid,

18
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
View File

@ -40,7 +40,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
input s_axi_awvalid, input s_axi_awvalid,
output s_axi_awready, output s_axi_awready,
input [11:0] s_axi_awaddr, input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot, input [2:0] s_axi_awprot,
input s_axi_wvalid, input s_axi_wvalid,
@ -50,7 +50,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
input s_axi_arvalid, input s_axi_arvalid,
output s_axi_arready, output s_axi_arready,
input [11:0] s_axi_araddr, input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot, input [2:0] s_axi_arprot,
output s_axi_rvalid, output s_axi_rvalid,
@ -106,11 +106,11 @@ module ad_ip_jesd204_tpl_dac_regmap #(
wire up_wreq_s; wire up_wreq_s;
wire [9:0] up_waddr_s; wire [10:0] up_waddr_s;
wire [31:0] up_wdata_s; wire [31:0] up_wdata_s;
wire [NUM_CHANNELS+1:0] up_wack_s; wire [NUM_CHANNELS+1:0] up_wack_s;
wire up_rreq_s; wire up_rreq_s;
wire [9:0] up_raddr_s; wire [10:0] up_raddr_s;
wire [31:0] up_rdata_s[0:NUM_CHANNELS+1]; wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
wire [NUM_CHANNELS+1:0] up_rack_s; wire [NUM_CHANNELS+1:0] up_rack_s;
@ -128,7 +128,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
// up bus interface // up bus interface
up_axi #( up_axi #(
.AXI_ADDRESS_WIDTH (12) .AXI_ADDRESS_WIDTH (13)
) i_up_axi ( ) i_up_axi (
.up_clk (up_clk), .up_clk (up_clk),
.up_rstn (up_rstn), .up_rstn (up_rstn),
@ -231,11 +231,11 @@ module ad_ip_jesd204_tpl_dac_regmap #(
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_wreq (up_wreq_s), .up_wreq (up_wreq_s),
.up_waddr ({4'b0,up_waddr_s}), .up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]), .up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s), .up_rreq (up_rreq_s),
.up_raddr ({4'b0,up_raddr_s}), .up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[0]), .up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]) .up_rack (up_rack_s[0])
); );
@ -282,11 +282,11 @@ module ad_ip_jesd204_tpl_dac_regmap #(
.up_clk (up_clk), .up_clk (up_clk),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_wreq (up_wreq_s), .up_wreq (up_wreq_s),
.up_waddr ({4'b0,up_waddr_s}), .up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_wack (up_wack_s[i+1]), .up_wack (up_wack_s[i+1]),
.up_rreq (up_rreq_s), .up_rreq (up_rreq_s),
.up_raddr ({4'b0,up_raddr_s}), .up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[i+1]), .up_rdata (up_rdata_s[i+1]),
.up_rack (up_rack_s[i+1]) .up_rack (up_rack_s[i+1])
); );