docs: page for AD3552R IP (#1323)
Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: PopPaul2021 <paul.pop@analog.com>main
PopPaul2021
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.. _axi_ad3552r:
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AXI AD3552R
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================================================================================
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.. hdl-component-diagram::
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The :git-hdl:`AXI AD3552R <library/axi_ad3552r>` IP core
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can be used to interface the :adi:`AD3552R`, a low drift, ultra-fast, 16-bit
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accuracy, current output digital-to-analog converter (DAC) that can be
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configured in multiple voltage span ranges.
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Features
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--------------------------------------------------------------------------------
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* AXI-based configuration
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* Vivado compatible
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* 8b register read/write SDR/DDR
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* 16b register read/write SDR/DDR
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* data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)
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* selectable input source: DMA/ADC/TEST_RAMP
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* data out clock(SCLK) has clk_in/8 frequency when the converter is configured and
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clk_in/2 when the converter is in stream mode
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* the IP reference clock (clk_in) can have a maximum frequency of 132MHz
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* the IP has multiple device synchronization capability when the DMA is set
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as an input data source
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/axi_ad3552r/axi_ad3552r.v`
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- Verilog source for the AXI AD3552R.
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* - :git-hdl:`library/axi_ad3552r/axi_ad3552r_channel.v`
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- Verilog source for the AXI AD3552R channel.
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* - :git-hdl:`library/axi_ad3552r/axi_ad3552r_core.v`
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- Verilog source for the AXI AD3552R core.
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* - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if.v`
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- Verilog source for the AD3552R interface module.
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* - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if_tb.v`
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- Verilog source for the AD3552R interface module testbench.
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* - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if_tb`
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- Setup script for the AD3552R interface module testbench.
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* - :git-hdl:`library/axi_ad3552r/axi_ad3552r_ip.tcl`
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- TCL script to generate the Vivado IP-integrator project.
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: block_diagram.svg
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:alt: AXI AD3552R block diagram
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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* - ID
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- Core ID should be unique for each IP in the system
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- 0
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* - FPGA_TECHNOLOGY
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- Encoded value describing the technology/generation of the FPGA device
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(Arria 10/7series)
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* - FPGA_FAMILY
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- Encoded value describing the family variant of the FPGA device(e.g., SX,
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GX, GT)
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* - SPEED_GRADE
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- Encoded value describing the FPGA's speed-grade
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* - DEV_PACKAGE
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- Encoded value describing the device package. The package might affect
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high-speed interfaces
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - dac_clk
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- Reference clock
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* - dma_data
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- Data from the DMAC when input source is set to DMA_DATA.
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* - valid_in_dma
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- Valid from the DMAC.
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* - dac_data_ready
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- Data ready signal for the DMAC.
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* - data_in_a
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- Data for channel 1 when input source is set to ADC_DATA.
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* - data_in_b
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- Data for channel 2 when input source is set to ADC_DATA.
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* - valid_in_a
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- Valid for channel 1.
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* - valid_in_b
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- Valid for channel 2.
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* - valid_in_dma_sec
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- Valid from a secondary DMAC if synchronization is needed.
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* - external_sync
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- External synchronization flag from another axi_ad3552r IP.
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* - sync_ext_device
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- Start_sync external device to another axi_ad3552r IP.
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* - dac_sclk
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- Serial clock.
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* - dac_csn
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- Serial chip select.
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* - sdio_o
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- Serial data out to the DAC.
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* - sdio_i
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- Serial data in from the DAC.
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* - sdio_t
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- I/O buffer control signal.
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* - s_axi
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- Standard AXI Slave Memory Map interface.
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Detailed Architecture
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--------------------------------------------------------------------------------
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.. image:: detailed_architecture.svg
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:alt: AXI AD3552R detailed architecture
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Detailed Description
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--------------------------------------------------------------------------------
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The top module instantiates:
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* The axi_ad3552r interface module
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* The axi_ad3552r core module
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* The AXI handling interface
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The axi_ad3552r_if has the state machine that controls the quad SPI interface.
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The axi_ad3552r_core module instantiates 2 axi_ad3552r channel modules.
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Register Map
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--------------------------------------------------------------------------------
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For the AXI_AD3552R control used registers from DAC Common are:
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.. hdl-regmap::
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:name: AXI_AD3552R_DAC_COMMON
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For the AXI_AD3552R control used registers from DAC Channel are:
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.. hdl-regmap::
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:name: AXI_AD3552R_DAC_CHANNEL
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For reference, all the register map templates are:
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.. hdl-regmap::
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:name: COMMON
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:no-type-info:
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.. hdl-regmap::
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:name: DAC_COMMON
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:no-type-info:
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.. hdl-regmap::
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:name: DAC_CHANNEL
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:no-type-info:
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Design Guidelines
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--------------------------------------------------------------------------------
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The control of the chip is done through the AXI_AD3552R IP.
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The *DAC interface* must be connected to an IO buffer.
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The example design uses a DMA to move the data from the memory to the CHIP quad
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SPI interface.
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If the data needs to be processed in HDL before moving to DAC's output, it can be
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done at the input of the IP (at the system level) or inside the axi_ad3552r_if
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interface module (at the IP level).
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The example design uses a processor to program all the registers. If no
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processor is available in your system, you can create your IP starting from the
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interface module.
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Software Guidelines
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--------------------------------------------------------------------------------
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Linux is supported using
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:dokuwiki:`AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver <resources/tools-software/linux-drivers/iio-dac/axi-ad3552r>`.
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References
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--------------------------------------------------------------------------------
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* :adi:`AD3552R`
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* :git-hdl:`projects/ad3552r_evb`
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* :git-hdl:`library/axi_ad3552r`
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* :git-linux:`/`
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* :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`
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* :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`
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TITLE
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USING DAC_COMMON
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AXI AD3552R DAC Common (axi_ad3552r_dac_common)
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AXI_AD3552R_DAC_COMMON
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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CNTRL_1
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ENDREG
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FIELD
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EXT_SYNC_ARM
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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CNTRL_2
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ENDREG
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FIELD
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SDR_DDR_N
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SYMB_8_16B
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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DAC_CUSTOM_WR
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ENDREG
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FIELD
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[23:0] 0x00000000
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DATA_WRITE
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RW
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Configuration data for the AD3552R device registers. 8/16 LSB are used depending on the
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8b/16b configuration.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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UI_STATUS
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ENDREG
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FIELD
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IF_BUSY
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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DAC_CUSTOM_CTRL
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ENDREG
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FIELD
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[31:24] 0x00000000
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ADDRESS
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RW
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Register address when the AD3552R is configured or stream start address when the
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FSM is in stream state.
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ENDFIELD
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FIELD
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[1] 0x00000000
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STREAM
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RW
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Setting this bit will trigger a stream transfer based on the SDR/DDR
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configuration and address.
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ENDFIELD
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FIELD
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[0] 0x00000000
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TRANSFER_DATA
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RW
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Setting this bit will trigger a single transfer based on the SDR/DDR,
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8b/16b configuration, address, and data_write.
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ENDFIELD
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############################################################################################
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############################################################################################
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TITLE
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USING DAC_CHANNEL
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AXI AD3552R DAC Channel (axi_ad3552r_dac_channel)
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AXI_AD3552R_DAC_CHANNEL
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0100
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CHAN_CNTRL0_7
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[3:0] 0x00000000
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DAC_DDS_SEL
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RW
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Select internal data sources (available only if the DAC supports it).
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* 0x00: internal tone (DDS)
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* 0x01: pattern (SED)
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* 0x02: input data (DMA)
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* 0x03: 0x00
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* 0x04: inverted pn7
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* 0x05: inverted pn15
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* 0x06: pn7 (standard O.150)
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* 0x07: pn15 (standard O.150)
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* 0x08: loopback data (ADC)
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* 0x09: pnX (Device specific e.g. ad9361)
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* 0x0A: Nibble ramp (Device specific e.g. adrv9001)
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* 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0116
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CHAN_CNTRL1_7
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DAC Channel Control & Status (channel - 1)
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ENDREG
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FIELD
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[3:0] 0x00000000
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DAC_DDS_SEL
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RW
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Select internal data sources (available only if the DAC supports it).
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* 0x00: internal tone (DDS)
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* 0x01: pattern (SED)
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* 0x02: input data (DMA)
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* 0x03: 0x00
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* 0x04: inverted pn7
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* 0x05: inverted pn15
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* 0x06: pn7 (standard O.150)
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* 0x07: pn15 (standard O.150)
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* 0x08: loopback data (ADC)
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* 0x09: pnX (Device specific e.g. ad9361)
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* 0x0A: Nibble ramp (Device specific e.g. adrv9001)
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* 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
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ENDFIELD
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############################################################################################
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############################################################################################
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