jesd204: Add Altera/Intel IP support
Add Qsys IP scripts as well as SDC constraint files for the ADI JESD204 peripherals. This allows them to be instantiated and used on Altera/Intel platforms. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
parent
d345a1e31a
commit
2d896c0729
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@ -0,0 +1,80 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
|
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# chips from Analog Devices, incorporate them into your PCB level product, and
|
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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set script_dir [file dirname [info script]]
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source "$script_dir/util_cdc_constr.tcl"
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util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_status}
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util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event}
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util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|sync_bits:i_cdc_status_ready}
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# set_max_skew?
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set_false_path \
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-to [get_registers {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|up_status_latency[*]}]
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util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|jesd204_up_ilas_mem:i_ilas_mem|sync_bits:i_cdc_ilas_ready}
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
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set_false_path \
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-to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
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set_false_path \
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-from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
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@ -0,0 +1,159 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
|
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# chips from Analog Devices, incorporate them into your PCB level product, and
|
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# purchase a JESD204 license, end users of your product will also have a
|
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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package require qsys
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
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ad_ip_create axi_jesd204_rx "ADI JESD204 Receive AXI Interface"
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set_module_property INTERNAL true
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# files
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ad_ip_files axi_jesd204_rx [list \
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axi_jesd204_rx.v \
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axi_jesd204_rx_constr.sdc \
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jesd204_up_rx.v \
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jesd204_up_rx_lane.v \
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jesd204_up_ilas_mem.v \
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../axi_jesd204_common/jesd204_up_common.v \
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../axi_jesd204_common/jesd204_up_sysref.v \
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$ad_hdl_dir/library/common/up_axi.v \
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$ad_hdl_dir/library/common/up_clock_mon.v \
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$ad_hdl_dir/library/util_cdc/sync_bits.v \
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$ad_hdl_dir/library/util_cdc/sync_data.v \
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$ad_hdl_dir/library/util_cdc/sync_event.v \
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$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
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$ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \
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]
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# parameters
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add_parameter ID NATURAL 0
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set_parameter_property ID DISPLAY_NAME "Peripheral ID"
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set_parameter_property ID HDL_PARAMETER true
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add_parameter NUM_LANES INTEGER 1
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set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
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set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
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set_parameter_property NUM_LANES HDL_PARAMETER true
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# axi4 slave interface
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14
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# interrupt
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add_interface interrupt interrupt end
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set_interface_property interrupt associatedClock s_axi_clock
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set_interface_property interrupt associatedReset s_axi_reset
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#set_interface_property interrupt associatedAddressablePoint s_axi
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add_interface_port interrupt irq irq Output 1
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# core clock
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add_interface core_clock clock end
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add_interface_port core_clock core_clk clk Input 1
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# core reset ext
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add_interface core_reset_ext reset end
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set_interface_property core_reset_ext associatedClock core_clock
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add_interface_port core_reset_ext core_reset_ext reset Input 1
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# core reset
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add_interface core_reset reset start
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set_interface_property core_reset associatedClock core_clock
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set_interface_property core_reset associatedResetSinks core_reset_ext
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add_interface_port core_reset core_reset reset Output 1
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# config interface
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add_interface config conduit end
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set_interface_property config associatedClock core_clock
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set_interface_property config associatedReset core_reset
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add_interface_port config core_cfg_beats_per_multiframe beats_per_multiframe Output 8
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add_interface_port config core_cfg_buffer_delay buffer_delay Output 8
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add_interface_port config core_cfg_buffer_early_release buffer_early_release Output 1
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add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
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add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
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add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
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add_interface_port config core_cfg_lmfc_offset lmfc_offset Output 8
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add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
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add_interface_port config core_cfg_sysref_disable sysref_disable Output 1
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add_interface_port config core_cfg_sysref_oneshot sysref_oneshot Output 1
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# status interface
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add_interface status conduit end
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set_interface_property status associatedClock core_clock
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set_interface_property status associatedReset core_reset
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add_interface_port status core_status_ctrl_state ctrl_state Input 3
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add_interface_port status core_status_lane_cgs_state lane_cgs_state Input 2*NUM_LANES
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add_interface_port status core_status_lane_ifs_ready lane_ifs_ready Input NUM_LANES
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add_interface_port status core_status_lane_latency lane_latency Input 14*NUM_LANES
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# event interface
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add_interface event conduit end
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set_interface_property event associatedClock core_clock
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set_interface_property event associatedReset core_reset
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add_interface_port event core_event_sysref_alignment_error sysref_alignment_error Input 1
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add_interface_port event core_event_sysref_edge sysref_edge Input 1
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# ilas_config
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add_interface ilas_config conduit end
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set_interface_property ilas_config associatedClock core_clock
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set_interface_property ilas_config associatedReset core_reset
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add_interface_port ilas_config core_ilas_config_addr addr Input 2*NUM_LANES
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add_interface_port ilas_config core_ilas_config_data data Input 32*NUM_LANES
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add_interface_port ilas_config core_ilas_config_valid valid Input NUM_LANES
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@ -0,0 +1,79 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
|
||||
#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
|
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# questions about and improve this core. Distribution of source, or resulting
|
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# binaries (including those inside an FPGA or ASIC) require you to release the
|
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# source of the entire project (excluding the system libraries provide by the
|
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
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# License version 2 as published by the Free Software Foundation.
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#
|
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
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# <http://www.gnu.org/licenses/>.
|
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
|
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# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
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# core with any corresponding source code.) For these alternate terms you must
|
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# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
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# source code).
|
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
|
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# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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set script_dir [file dirname [info script]]
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source "$script_dir/util_cdc_constr.tcl"
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util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event}
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util_cdc_sync_event_constr {*|jesd204_up_tx:i_up_tx|sync_event:i_cdc_manual_sync_request}
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util_cdc_sync_data_constr {*|jesd204_up_tx:i_up_tx|sync_data:i_cdc_status}
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util_cdc_sync_bits_constr {*|jesd204_up_tx:i_up_tx|sync_bits:i_cdc_sync}
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
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set_false_path \
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-to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
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set_false_path \
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-from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_ilas_data_*}] \
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-to [get_registers {*|jesd204_up_tx:i_up_tx|core_ilas_config_data[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
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@ -0,0 +1,165 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
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package require qsys
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source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
|
||||
|
||||
ad_ip_create axi_jesd204_tx "ADI JESD204 Transmit AXI Interface"
|
||||
|
||||
set_module_property INTERNAL true
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files axi_jesd204_tx [list \
|
||||
axi_jesd204_tx.v \
|
||||
axi_jesd204_tx_constr.sdc \
|
||||
jesd204_up_tx.v \
|
||||
../axi_jesd204_common/jesd204_up_common.v \
|
||||
../axi_jesd204_common/jesd204_up_sysref.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_data.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_event.v \
|
||||
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
|
||||
$ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID NATURAL 0
|
||||
set_parameter_property ID DISPLAY_NAME "Peripheral ID"
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter NUM_LANES INTEGER 1
|
||||
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
|
||||
set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LANES HDL_PARAMETER true
|
||||
|
||||
# axi4 slave interface
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14
|
||||
|
||||
# interrupt
|
||||
|
||||
add_interface interrupt interrupt end
|
||||
set_interface_property interrupt associatedClock s_axi_clock
|
||||
set_interface_property interrupt associatedReset s_axi_reset
|
||||
#set_interface_property interrupt associatedAddressablePoint s_axi
|
||||
add_interface_port interrupt irq irq Output 1
|
||||
|
||||
# core clock
|
||||
|
||||
add_interface core_clock clock end
|
||||
add_interface_port core_clock core_clk clk Input 1
|
||||
|
||||
# core reset ext
|
||||
|
||||
add_interface core_reset_ext reset end
|
||||
set_interface_property core_reset_ext associatedClock core_clock
|
||||
add_interface_port core_reset_ext core_reset_ext reset Input 1
|
||||
|
||||
# core reset
|
||||
|
||||
add_interface core_reset reset start
|
||||
set_interface_property core_reset associatedClock core_clock
|
||||
set_interface_property core_reset associatedResetSinks core_reset_ext
|
||||
add_interface_port core_reset core_reset reset Output 1
|
||||
|
||||
# config interface
|
||||
|
||||
add_interface config conduit end
|
||||
set_interface_property config associatedClock core_clock
|
||||
set_interface_property config associatedReset core_reset
|
||||
|
||||
add_interface_port config core_cfg_beats_per_multiframe beats_per_multiframe Output 8
|
||||
add_interface_port config core_cfg_continuous_cgs continuous_cgs Output 1
|
||||
add_interface_port config core_cfg_continuous_ilas continuous_ilas Output 1
|
||||
add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
|
||||
add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
|
||||
add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
|
||||
add_interface_port config core_cfg_lmfc_offset lmfc_offset Output 8
|
||||
add_interface_port config core_cfg_mframes_per_ilas mframes_per_ilas Output 8
|
||||
add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
|
||||
add_interface_port config core_cfg_skip_ilas skip_ilas Output 1
|
||||
add_interface_port config core_cfg_sysref_disable sysref_disable Output 1
|
||||
add_interface_port config core_cfg_sysref_oneshot sysref_oneshot Output 1
|
||||
|
||||
# control interface
|
||||
|
||||
add_interface control conduit end
|
||||
set_interface_property control associatedClock core_clock
|
||||
set_interface_property control associatedReset core_reset
|
||||
|
||||
add_interface_port control core_ctrl_manual_sync_request manual_sync_request Output 1
|
||||
|
||||
# ilas config interface
|
||||
|
||||
add_interface ilas_config conduit end
|
||||
set_interface_property ilas_config associatedClock core_clock
|
||||
set_interface_property ilas_config associatedReset core_reset
|
||||
|
||||
add_interface_port ilas_config core_ilas_config_addr addr Input 2
|
||||
add_interface_port ilas_config core_ilas_config_data data Output 32*NUM_LANES
|
||||
add_interface_port ilas_config core_ilas_config_rd rd Input 1
|
||||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock core_clock
|
||||
set_interface_property event associatedReset core_reset
|
||||
|
||||
add_interface_port event core_event_sysref_alignment_error sysref_alignment_error Input 1
|
||||
add_interface_port event core_event_sysref_edge sysref_edge Input 1
|
||||
|
||||
# status interface
|
||||
|
||||
add_interface status conduit end
|
||||
set_interface_property status associatedClock core_clock
|
||||
set_interface_property status associatedReset core_reset
|
||||
|
||||
add_interface_port status core_status_state state Input 2
|
||||
add_interface_port status core_status_sync sync Input 1
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
# SYNC~ is a asynchronous interface
|
||||
set_false_path \
|
||||
-from [get_registers *|jesd204_rx_ctrl:i_rx_ctrl|sync_n]
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
package require qsys
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
|
||||
|
||||
ad_ip_create jesd204_rx "ADI JESD204 Receive" jesd204_rx_elaboration_callback
|
||||
|
||||
set_module_property INTERNAL true
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files jesd204_rx [list \
|
||||
rx.v \
|
||||
align_mux.v \
|
||||
elastic_buffer.v \
|
||||
ilas_monitor.v \
|
||||
lane_latency_monitor.v \
|
||||
rx_cgs.v \
|
||||
rx_ctrl.v \
|
||||
rx_lane.v \
|
||||
jesd204_rx_constr.sdc \
|
||||
../jesd204_common/eof.v \
|
||||
../jesd204_common/lmfc.v \
|
||||
../jesd204_common/scrambler.v \
|
||||
../jesd204_common/pipeline_stage.v \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter NUM_LANES INTEGER 1
|
||||
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
|
||||
set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LANES HDL_PARAMETER true
|
||||
|
||||
#ad_ip_parameter PORT_ENABLE_RX_EOF BOOLEAN false false
|
||||
#ad_ip_parameter PORT_ENABLE_LMFC_CLK BOOLEAN false false
|
||||
#ad_ip_parameter PORT_ENABLE_LMFC_EDGE BOOLEAN false false
|
||||
|
||||
# clock
|
||||
|
||||
add_interface clock clock end
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
# reset
|
||||
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
# SYSREF~ interface
|
||||
|
||||
add_interface sysref conduit end
|
||||
set_interface_property sysref associatedClock clock
|
||||
set_interface_property sysref associatedReset reset
|
||||
add_interface_port sysref sysref export Input 1
|
||||
|
||||
# SYNC interface
|
||||
|
||||
add_interface sync conduit end
|
||||
set_interface_property sync associatedClock clock
|
||||
set_interface_property sync associatedReset reset
|
||||
add_interface_port sync sync export Output 1
|
||||
|
||||
# config interface
|
||||
|
||||
add_interface config conduit end
|
||||
set_interface_property config associatedClock clock
|
||||
set_interface_property config associatedReset reset
|
||||
|
||||
add_interface_port config cfg_beats_per_multiframe beats_per_multiframe Input 8
|
||||
add_interface_port config cfg_buffer_delay buffer_delay Input 8
|
||||
add_interface_port config cfg_buffer_early_release buffer_early_release Input 1
|
||||
add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1
|
||||
add_interface_port config cfg_disable_scrambler disable_scrambler Input 1
|
||||
add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES
|
||||
add_interface_port config cfg_lmfc_offset lmfc_offset Input 8
|
||||
add_interface_port config cfg_octets_per_frame octets_per_frame Input 8
|
||||
add_interface_port config cfg_sysref_disable sysref_disable Input 1
|
||||
add_interface_port config cfg_sysref_oneshot sysref_oneshot Input 1
|
||||
|
||||
# status interface
|
||||
|
||||
add_interface status conduit end
|
||||
set_interface_property status associatedClock clock
|
||||
set_interface_property status associatedReset reset
|
||||
|
||||
add_interface_port status status_ctrl_state ctrl_state Output 3
|
||||
add_interface_port status status_lane_cgs_state lane_cgs_state Output 2*NUM_LANES
|
||||
add_interface_port status status_lane_ifs_ready lane_ifs_ready Output NUM_LANES
|
||||
add_interface_port status status_lane_latency lane_latency Output 14*NUM_LANES
|
||||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock clock
|
||||
set_interface_property event associatedReset reset
|
||||
|
||||
add_interface_port event event_sysref_alignment_error sysref_alignment_error Output 1
|
||||
add_interface_port event event_sysref_edge sysref_edge Output 1
|
||||
|
||||
# ilas_config interface
|
||||
|
||||
add_interface ilas_config conduit end
|
||||
set_interface_property ilas_config associatedClock clock
|
||||
set_interface_property ilas_config associatedReset reset
|
||||
|
||||
add_interface_port ilas_config ilas_config_addr addr Output NUM_LANES*2
|
||||
add_interface_port ilas_config ilas_config_data data Output NUM_LANES*32
|
||||
add_interface_port ilas_config ilas_config_valid valid Output NUM_LANES
|
||||
|
||||
# rx_eof interface
|
||||
|
||||
add_interface rx_eof conduit end
|
||||
#set_interface_property rx_eof associatedClock clock
|
||||
#set_interface_property rx_eof associatedReset reset
|
||||
add_interface_port rx_eof rx_eof export Output 4
|
||||
set_port_property rx_eof TERMINATION TRUE
|
||||
|
||||
# rx_sof interface
|
||||
|
||||
add_interface rx_sof conduit end
|
||||
#set_interface_property rx_sof associatedClock clock
|
||||
#set_interface_property rx_sof associatedReset reset
|
||||
add_interface_port rx_sof rx_sof export Output 4
|
||||
|
||||
# lmfc_clk interface
|
||||
|
||||
add_interface lmfc_clk conduit end
|
||||
#set_interface_property lmfc_clk associatedClock clock
|
||||
#set_interface_property lmfc_clk associatedReset reset
|
||||
add_interface_port lmfc_clk lmfc_clk export Output 1
|
||||
set_port_property lmfc_clk TERMINATION TRUE
|
||||
|
||||
# lmfc_edge interface
|
||||
|
||||
add_interface lmfc_edge conduit end
|
||||
#set_interface_property lmfc_edge associatedClock clock
|
||||
#set_interface_property lmfc_edge associatedReset reset
|
||||
add_interface_port lmfc_edge lmfc_edge export Output 1
|
||||
set_port_property lmfc_edge TERMINATION TRUE
|
||||
|
||||
proc jesd204_rx_elaboration_callback {} {
|
||||
set num_lanes [get_parameter_value "NUM_LANES"]
|
||||
|
||||
# rx_data interface
|
||||
|
||||
add_interface rx_data avalon_streaming source
|
||||
set_interface_property rx_data associatedClock clock
|
||||
|
||||
add_interface_port rx_data rx_data data output [expr 32*$num_lanes]
|
||||
add_interface_port rx_data rx_valid valid output 1
|
||||
set_interface_property rx_data dataBitsPerSymbol [expr 32*$num_lanes]
|
||||
|
||||
# phy interfaces
|
||||
|
||||
for {set i 0 } {$i < $num_lanes} {incr i} {
|
||||
add_interface rx_phy${i} conduit end
|
||||
# set_interface_property rx_phy${i} associatedClock clock
|
||||
# set_interface_property rx_phy${i} associatedReset reset
|
||||
add_interface_port rx_phy${i} rx_phy${i}_data char Input 32
|
||||
set_port_property rx_phy${i}_data fragment_list \
|
||||
[format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]]
|
||||
add_interface_port rx_phy${i} rx_phy${i}_charisk charisk Input 4
|
||||
set_port_property rx_phy${i}_charisk fragment_list \
|
||||
[format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
|
||||
add_interface_port rx_phy${i} rx_phy${i}_disperr disperr Input 4
|
||||
set_port_property rx_phy${i}_disperr fragment_list \
|
||||
[format "phy_disperr(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
|
||||
add_interface_port rx_phy${i} rx_phy${i}_notintable notintable Input 4
|
||||
set_port_property rx_phy${i}_notintable fragment_list \
|
||||
[format "phy_notintable(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
|
||||
add_interface_port rx_phy${i} rx_phy${i}_patternalign_en patternalign_en Output 1
|
||||
set_port_property rx_phy${i}_patternalign_en fragment_list "phy_en_char_align"
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
source "$script_dir/util_cdc_constr.tcl"
|
||||
|
||||
# SYNC~ is a asynchronous interface
|
||||
util_cdc_sync_bits_constr {*|jesd204_tx_ctrl:i_tx_ctrl|sync_bits:i_cdc_sync}
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
package require qsys
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
|
||||
|
||||
ad_ip_create jesd204_tx "ADI JESD204 Transmit" jesd204_tx_elaboration_callback
|
||||
|
||||
set_module_property INTERNAL true
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files jesd204_tx [list \
|
||||
tx.v \
|
||||
tx_ctrl.v \
|
||||
tx_lane.v \
|
||||
jesd204_tx_constr.sdc \
|
||||
../jesd204_common/eof.v \
|
||||
../jesd204_common/lmfc.v \
|
||||
../jesd204_common/scrambler.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter NUM_LANES INTEGER 1
|
||||
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
|
||||
set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LANES HDL_PARAMETER true
|
||||
|
||||
# clock
|
||||
|
||||
add_interface clock clock end
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
# reset
|
||||
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
# SYSREF~ interface
|
||||
|
||||
add_interface sysref conduit end
|
||||
set_interface_property sysref associatedClock clock
|
||||
set_interface_property sysref associatedReset reset
|
||||
add_interface_port sysref sysref export Input 1
|
||||
|
||||
# SYNC interface
|
||||
|
||||
add_interface sync conduit end
|
||||
set_interface_property sync associatedClock clock
|
||||
set_interface_property sync associatedReset reset
|
||||
add_interface_port sync sync export Input 1
|
||||
|
||||
# ilas_config interface
|
||||
|
||||
add_interface ilas_config conduit end
|
||||
set_interface_property ilas_config associatedClock clock
|
||||
set_interface_property ilas_config associatedReset reset
|
||||
|
||||
add_interface_port ilas_config ilas_config_addr addr Output 2
|
||||
add_interface_port ilas_config ilas_config_data data Input 32*NUM_LANES
|
||||
add_interface_port ilas_config ilas_config_rd rd Output 1
|
||||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock clock
|
||||
set_interface_property event associatedReset reset
|
||||
|
||||
add_interface_port event event_sysref_alignment_error sysref_alignment_error Output 1
|
||||
add_interface_port event event_sysref_edge sysref_edge Output 1
|
||||
|
||||
# control interface
|
||||
|
||||
add_interface control conduit end
|
||||
set_interface_property control associatedClock clock
|
||||
set_interface_property control associatedReset reset
|
||||
|
||||
add_interface_port control ctrl_manual_sync_request manual_sync_request Input 1
|
||||
|
||||
# config interface
|
||||
|
||||
add_interface config conduit end
|
||||
set_interface_property config associatedClock clock
|
||||
set_interface_property config associatedReset reset
|
||||
|
||||
add_interface_port config cfg_beats_per_multiframe beats_per_multiframe Input 8
|
||||
add_interface_port config cfg_continuous_cgs continuous_cgs Input 1
|
||||
add_interface_port config cfg_continuous_ilas continuous_ilas Input 1
|
||||
add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1
|
||||
add_interface_port config cfg_disable_scrambler disable_scrambler Input 1
|
||||
add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES
|
||||
add_interface_port config cfg_lmfc_offset lmfc_offset Input 8
|
||||
add_interface_port config cfg_mframes_per_ilas mframes_per_ilas Input 8
|
||||
add_interface_port config cfg_octets_per_frame octets_per_frame Input 8
|
||||
add_interface_port config cfg_skip_ilas skip_ilas Input 1
|
||||
add_interface_port config cfg_sysref_disable sysref_disable Input 1
|
||||
add_interface_port config cfg_sysref_oneshot sysref_oneshot Input 1
|
||||
|
||||
# status interface
|
||||
|
||||
add_interface status conduit end
|
||||
set_interface_property status associatedClock clock
|
||||
set_interface_property status associatedReset reset
|
||||
|
||||
add_interface_port status status_state state Output 2
|
||||
add_interface_port status status_sync sync Output 1
|
||||
|
||||
# lmfc_clk interface
|
||||
|
||||
add_interface lmfc_clk conduit end
|
||||
#set_interface_property lmfc_clk associatedClock clock
|
||||
#set_interface_property lmfc_clk associatedReset reset
|
||||
add_interface_port lmfc_clk lmfc_clk export Output 1
|
||||
set_port_property lmfc_clk TERMINATION TRUE
|
||||
|
||||
# lmfc_edge interface
|
||||
|
||||
add_interface lmfc_edge conduit end
|
||||
#set_interface_property lmfc_edge associatedClock clock
|
||||
#set_interface_property lmfc_edge associatedReset reset
|
||||
add_interface_port lmfc_edge lmfc_edge export Output 1
|
||||
set_port_property lmfc_edge TERMINATION TRUE
|
||||
|
||||
proc jesd204_tx_elaboration_callback {} {
|
||||
set num_lanes [get_parameter_value "NUM_LANES"]
|
||||
|
||||
# tx_data interface
|
||||
|
||||
add_interface tx_data avalon_streaming sink
|
||||
set_interface_property tx_data associatedClock clock
|
||||
|
||||
add_interface_port tx_data tx_data data input [expr 32*$num_lanes]
|
||||
add_interface_port tx_data tx_ready ready output 1
|
||||
add_interface_port tx_data tx_valid valid input 1
|
||||
set_interface_property tx_data dataBitsPerSymbol [expr 32*$num_lanes]
|
||||
|
||||
# phy interfaces
|
||||
|
||||
for {set i 0 } {$i < $num_lanes} {incr i} {
|
||||
add_interface tx_phy${i} conduit start
|
||||
# set_interface_property tx_phy${i} associatedClock clock
|
||||
# set_interface_property tx_phy${i} associatedReset reset
|
||||
add_interface_port tx_phy${i} tx_phy${i}_data char Output 32
|
||||
set_port_property tx_phy${i}_data fragment_list \
|
||||
[format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]]
|
||||
add_interface_port tx_phy${i} tx_phy${i}_charisk charisk Output 4
|
||||
set_port_property tx_phy${i}_charisk fragment_list \
|
||||
[format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue