axi_ad9122: Update for CORDIC algorithm integration
Add the new files to the IP list Propagate DDS parameters to top filemain
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4362c35125
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2daca03665
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@ -47,6 +47,8 @@ module axi_ad9122 #(
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parameter MMCM_CLK0_DIV = 2,
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parameter MMCM_CLK1_DIV = 8,
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parameter DAC_DATAPATH_DISABLE = 0,
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parameter DAC_DDS_TYPE = 1,
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parameter DAC_DDS_CORDIC_DW = 16,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// dac interface
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@ -201,7 +203,12 @@ module axi_ad9122 #(
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// core
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axi_ad9122_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
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axi_ad9122_core #(
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.ID(ID),
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.DDS_TYPE (DAC_DDS_TYPE),
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.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
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.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
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i_core (
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.dac_div_clk (dac_div_clk),
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.dac_rst (dac_rst),
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.dac_frame_i0 (dac_frame_i0_s),
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@ -38,6 +38,8 @@
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module axi_ad9122_channel #(
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parameter CHANNEL_ID = 32'h0,
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parameter DDS_TYPE = 1,
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parameter DDS_CORDIC_DW = 16,
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parameter DATAPATH_DISABLE = 0) (
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// dac interface
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@ -151,7 +153,11 @@ module axi_ad9122_channel #(
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if (DATAPATH_DISABLE == 1) begin
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assign dac_dds_data_0_s = 16'd0;
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end else begin
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ad_dds i_dds_0 (
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ad_dds #(
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.DISABLE (0),
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.DDS_TYPE (DDS_TYPE),
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.CORDIC_DW (DDS_CORDIC_DW))
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i_dds_0 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_0_0),
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@ -166,7 +172,11 @@ module axi_ad9122_channel #(
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if (DATAPATH_DISABLE == 1) begin
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assign dac_dds_data_1_s = 16'd0;
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end else begin
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ad_dds i_dds_1 (
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ad_dds #(
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.DISABLE (0),
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.DDS_TYPE (DDS_TYPE),
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.CORDIC_DW (DDS_CORDIC_DW))
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i_dds_1 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_1_0),
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@ -181,7 +191,11 @@ module axi_ad9122_channel #(
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if (DATAPATH_DISABLE == 1) begin
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assign dac_dds_data_2_s = 16'd0;
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end else begin
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ad_dds i_dds_2 (
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ad_dds #(
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.DISABLE (0),
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.DDS_TYPE (DDS_TYPE),
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.CORDIC_DW (DDS_CORDIC_DW))
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i_dds_2 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_2_0),
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@ -196,7 +210,11 @@ module axi_ad9122_channel #(
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if (DATAPATH_DISABLE == 1) begin
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assign dac_dds_data_3_s = 16'd0;
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end else begin
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ad_dds i_dds_3 (
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ad_dds #(
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.DISABLE (0),
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.DDS_TYPE (DDS_TYPE),
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.CORDIC_DW (DDS_CORDIC_DW))
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i_dds_3 (
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.clk (dac_div_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_3_0),
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@ -38,6 +38,8 @@
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module axi_ad9122_core #(
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parameter ID = 0,
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parameter DDS_TYPE = 1,
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parameter DDS_CORDIC_DW = 16,
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parameter DATAPATH_DISABLE = 0) (
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// dac interface
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@ -149,6 +151,8 @@ module axi_ad9122_core #(
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axi_ad9122_channel #(
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.CHANNEL_ID(0),
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.DDS_TYPE (DDS_TYPE),
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.DDS_CORDIC_DW (DDS_CORDIC_DW),
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.DATAPATH_DISABLE(DATAPATH_DISABLE))
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i_channel_0 (
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.dac_div_clk (dac_div_clk),
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@ -175,6 +179,8 @@ module axi_ad9122_core #(
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axi_ad9122_channel #(
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.CHANNEL_ID(1),
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.DDS_TYPE (DDS_TYPE),
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.DDS_CORDIC_DW (DDS_CORDIC_DW),
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.DATAPATH_DISABLE(DATAPATH_DISABLE))
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i_channel_1 (
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.dac_div_clk (dac_div_clk),
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@ -6,6 +6,8 @@ source ../scripts/adi_ip_alt.tcl
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ad_ip_create axi_ad9122 {AXI AD9122 Interface}
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ad_ip_files axi_ad9122 [list \
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$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
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$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
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$ad_hdl_dir/library/common/ad_dds_sine.v \
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$ad_hdl_dir/library/common/ad_dds_1.v \
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$ad_hdl_dir/library/common/ad_dds.v \
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@ -6,6 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_ad9122
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adi_ip_files axi_ad9122 [list \
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"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
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"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
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"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
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"$ad_hdl_dir/library/common/ad_dds_sine.v" \
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"$ad_hdl_dir/library/common/ad_dds_1.v" \
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"$ad_hdl_dir/library/common/ad_dds.v" \
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