axi_ad9122: Update for CORDIC algorithm integration

Add the new files to the IP list
Propagate DDS parameters to top file
main
AndreiGrozav 2018-02-07 14:10:27 +02:00 committed by AndreiGrozav
parent 4362c35125
commit 2daca03665
5 changed files with 40 additions and 5 deletions

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@ -47,6 +47,8 @@ module axi_ad9122 #(
parameter MMCM_CLK0_DIV = 2,
parameter MMCM_CLK1_DIV = 8,
parameter DAC_DATAPATH_DISABLE = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// dac interface
@ -201,7 +203,12 @@ module axi_ad9122 #(
// core
axi_ad9122_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core (
axi_ad9122_core #(
.ID(ID),
.DDS_TYPE (DAC_DDS_TYPE),
.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_frame_i0 (dac_frame_i0_s),

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@ -38,6 +38,8 @@
module axi_ad9122_channel #(
parameter CHANNEL_ID = 32'h0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DATAPATH_DISABLE = 0) (
// dac interface
@ -151,7 +153,11 @@ module axi_ad9122_channel #(
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
@ -166,7 +172,11 @@ module axi_ad9122_channel #(
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
i_dds_1 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
@ -181,7 +191,11 @@ module axi_ad9122_channel #(
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
i_dds_2 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_2_0),
@ -196,7 +210,11 @@ module axi_ad9122_channel #(
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
i_dds_3 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_3_0),

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@ -38,6 +38,8 @@
module axi_ad9122_core #(
parameter ID = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DATAPATH_DISABLE = 0) (
// dac interface
@ -149,6 +151,8 @@ module axi_ad9122_core #(
axi_ad9122_channel #(
.CHANNEL_ID(0),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_0 (
.dac_div_clk (dac_div_clk),
@ -175,6 +179,8 @@ module axi_ad9122_core #(
axi_ad9122_channel #(
.CHANNEL_ID(1),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_1 (
.dac_div_clk (dac_div_clk),

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@ -6,6 +6,8 @@ source ../scripts/adi_ip_alt.tcl
ad_ip_create axi_ad9122 {AXI AD9122 Interface}
ad_ip_files axi_ad9122 [list \
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_1.v \
$ad_hdl_dir/library/common/ad_dds.v \

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@ -6,6 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9122
adi_ip_files axi_ad9122 [list \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \