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axi_pwm_gen: add: intel support (#1080) 

Signed-off-by: Jem Geronimo <johnerasmusmari.geronimo@analog.com>
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Jem Geronimo 2023-02-07 18:27:04 +08:00 committed by GitHub
parent a8a01aaaf4
commit 2db944396f
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2 changed files with 53 additions and 0 deletions
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3
library/axi_pwm_gen/Makefile
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@ -18,4 +18,7 @@ XILINX_DEPS += axi_pwm_gen_ip.tcl
XILINX_LIB_DEPS += util_cdc
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
INTEL_DEPS += axi_pwm_gen_hw.tcl
include ../scripts/library.mk

50
library/axi_pwm_gen/axi_pwm_gen_hw.tcl Normal file
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@ -0,0 +1,50 @@
# ip
package require qsys 14.0
package require quartus::device
source ../../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
ad_ip_create axi_pwm_gen {AXI PWM GEN}
ad_ip_files axi_pwm_gen [list \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
axi_pwm_gen_regmap.v \
axi_pwm_gen_1.v \
axi_pwm_gen.v]
# parameters
ad_ip_parameter ID INTEGER 0
ad_ip_parameter ASYNC_CLK_EN INTEGER 1
ad_ip_parameter N_PWMS INTEGER 1
ad_ip_parameter PWM_EXT_SYNC INTEGER 0
ad_ip_parameter EXT_ASYNC_SYNC INTEGER 0
ad_ip_parameter PULSE_0_WIDTH INTEGER 7
ad_ip_parameter PULSE_1_WIDTH INTEGER 7
ad_ip_parameter PULSE_2_WIDTH INTEGER 7
ad_ip_parameter PULSE_3_WIDTH INTEGER 7
ad_ip_parameter PULSE_0_PERIOD INTEGER 10
ad_ip_parameter PULSE_1_PERIOD INTEGER 10
ad_ip_parameter PULSE_2_PERIOD INTEGER 10
ad_ip_parameter PULSE_3_PERIOD INTEGER 10
ad_ip_parameter PULSE_0_OFFSET INTEGER 0
ad_ip_parameter PULSE_1_OFFSET INTEGER 0
ad_ip_parameter PULSE_2_OFFSET INTEGER 0
ad_ip_parameter PULSE_3_OFFSET INTEGER 0
# interfaces
# axi
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
# external clock and external sync
ad_interface clock ext_clk input 1
ad_interface signal ext_sync input 1
# output signals
for {set i 0} {$i < 4} {incr i} {
ad_interface signal pwm_$i output 1
}