ad9361_tdd: Some naming and hierarchical changes
parent
47469ad375
commit
2e877389b2
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@ -313,8 +313,6 @@ module axi_ad9361 (
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wire dac_valid_i1_s;
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wire dac_valid_i1_s;
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wire dac_valid_q1_s;
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wire dac_valid_q1_s;
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wire tdd_mode_enable_s;
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// signal name changes
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_clk = s_axi_aclk;
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@ -394,13 +392,20 @@ module axi_ad9361 (
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axi_ad9361_tdd i_tdd(
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axi_ad9361_tdd i_tdd(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.tdd_enable(tdd_mode_enable_s),
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.tdd_tx_dp_en(tdd_tx_dp_en_s),
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.tdd_tx_dp_en(tdd_tx_dp_en_s),
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.tdd_rx_vco_en(tdd_rx_vco_en_s),
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.tdd_rx_vco_en(tdd_rx_vco_en_s),
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.tdd_tx_vco_en(tdd_tx_vco_en_s),
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.tdd_tx_vco_en(tdd_tx_vco_en_s),
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.tdd_rx_rf_en(tdd_rx_rf_en_s),
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.tdd_rx_rf_en(tdd_rx_rf_en_s),
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.tdd_tx_rf_en(tdd_tx_rf_en_s),
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.tdd_tx_rf_en(tdd_tx_rf_en_s),
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.tdd_status(tdd_status_s),
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.tdd_status(tdd_status_s),
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.tx_valid_i0(dac_valid_i0_s),
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.tx_valid_q0(dac_valid_q0_s),
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.tx_valid_i1(dac_valid_i1_s),
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.tx_valid_q1(dac_valid_q1_s),
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.tdd_tx_valid_i0(dac_valid_i0),
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.tdd_tx_valid_q0(dac_valid_q0),
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.tdd_tx_valid_i1(dac_valid_i1),
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.tdd_tx_valid_q1(dac_valid_q1),
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.up_rstn(up_rstn),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_clk(up_clk),
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.up_wreq(up_wreq_s),
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.up_wreq(up_wreq_s),
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@ -414,6 +419,7 @@ module axi_ad9361 (
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.tdd_dbg(tdd_dbg)
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.tdd_dbg(tdd_dbg)
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);
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);
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// receive
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// receive
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axi_ad9361_rx #(
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axi_ad9361_rx #(
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@ -507,11 +513,6 @@ module axi_ad9361 (
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.up_rdata (up_rdata_tx_s),
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.up_rdata (up_rdata_tx_s),
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.up_rack (up_rack_tx_s));
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.up_rack (up_rack_tx_s));
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assign dac_valid_i0 = (tdd_mode_enable_s == 1) ? (dac_valid_i0_s & tdd_tx_dp_en_s) : dac_valid_i0_s;
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assign dac_valid_q0 = (tdd_mode_enable_s == 1) ? (dac_valid_q0_s & tdd_tx_dp_en_s) : dac_valid_q0_s;
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assign dac_valid_i1 = (tdd_mode_enable_s == 1) ? (dac_valid_i1_s & tdd_tx_dp_en_s) : dac_valid_i1_s;
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assign dac_valid_q1 = (tdd_mode_enable_s == 1) ? (dac_valid_q1_s & tdd_tx_dp_en_s) : dac_valid_q1_s;
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// axi interface
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// axi interface
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up_axi i_up_axi (
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up_axi i_up_axi (
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@ -48,7 +48,6 @@ module axi_ad9361_tdd (
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// control signals from the tdd control
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// control signals from the tdd control
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tdd_enable,
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tdd_tx_dp_en,
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tdd_tx_dp_en,
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tdd_rx_vco_en,
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tdd_rx_vco_en,
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tdd_tx_vco_en,
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tdd_tx_vco_en,
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@ -59,6 +58,18 @@ module axi_ad9361_tdd (
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tdd_status,
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tdd_status,
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// tx data flow control
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tx_valid_i0,
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tx_valid_q0,
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tx_valid_i1,
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tx_valid_q1,
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tdd_tx_valid_i0,
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tdd_tx_valid_q0,
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tdd_tx_valid_i1,
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tdd_tx_valid_q1,
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// bus interface
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// bus interface
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up_rstn,
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up_rstn,
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@ -80,7 +91,6 @@ module axi_ad9361_tdd (
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// control signals from the tdd control
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// control signals from the tdd control
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output tdd_enable;
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output tdd_tx_dp_en;
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output tdd_tx_dp_en;
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output tdd_rx_vco_en;
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output tdd_rx_vco_en;
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output tdd_tx_vco_en;
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output tdd_tx_vco_en;
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@ -89,6 +99,18 @@ module axi_ad9361_tdd (
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input [ 7:0] tdd_status;
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input [ 7:0] tdd_status;
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// tx data flow control
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input tx_valid_i0;
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input tx_valid_q0;
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input tx_valid_i1;
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input tx_valid_q1;
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output tdd_tx_valid_i0;
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output tdd_tx_valid_q0;
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output tdd_tx_valid_i1;
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output tdd_tx_valid_q1;
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// bus interface
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// bus interface
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input up_rstn;
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input up_rstn;
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@ -110,8 +132,8 @@ module axi_ad9361_tdd (
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wire tdd_enable_s;
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wire tdd_enable_s;
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wire tdd_secondary_s;
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wire tdd_secondary_s;
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wire [ 7:0] tdd_burst_count_s;
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wire [ 7:0] tdd_burst_count_s;
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wire tdd_txnrx_only_en_s;
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wire tdd_rx_only_s;
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wire tdd_txnrx_only_s;
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wire tdd_tx_only_s;
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wire [23:0] tdd_counter_init_s;
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wire [23:0] tdd_counter_init_s;
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wire [23:0] tdd_frame_length_s;
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wire [23:0] tdd_frame_length_s;
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wire [23:0] tdd_vco_rx_on_1_s;
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wire [23:0] tdd_vco_rx_on_1_s;
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@ -137,10 +159,15 @@ module axi_ad9361_tdd (
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wire [23:0] tdd_counter_status;
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wire [23:0] tdd_counter_status;
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assign tdd_dbg = {tdd_counter_status, tdd_enable, tdd_tx_dp_en,
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assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_tx_dp_en,
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tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
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tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
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assign tdd_enable = tdd_enable_s;
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// tx data flow control
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assign tdd_tx_valid_i0 = tx_valid_i0 & tdd_enable_s;
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assign tdd_tx_valid_q0 = tx_valid_q0 & tdd_enable_s;
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assign tdd_tx_valid_i1 = tx_valid_i1 & tdd_enable_s;
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assign tdd_tx_valid_q1 = tx_valid_q1 & tdd_enable_s;
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// instantiations
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// instantiations
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@ -150,8 +177,8 @@ module axi_ad9361_tdd (
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.tdd_enable(tdd_enable_s),
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.tdd_enable(tdd_enable_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_txnrx_only_en(tdd_txnrx_only_en_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_txnrx_only(tdd_txnrx_only_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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@ -194,8 +221,8 @@ module axi_ad9361_tdd (
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_txnrx_only_en(tdd_txnrx_only_en_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_txnrx_only(tdd_txnrx_only_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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@ -37,8 +37,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// A simple adder/substracter width preconfigured input ports width and overflow value
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// A simple adder/substracter width preconfigured input ports width and turn-around value
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// Output = A - B or A + B
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// Output = A - B_constant or A + B_constant
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// Constraints: Awidth >= Bwidth
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// Constraints: Awidth >= Bwidth
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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@ -46,7 +46,7 @@
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module ad_addsub (
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module ad_addsub (
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clk,
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clk,
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A,
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A,
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overflow,
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Amax,
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out,
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out,
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CE
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CE
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);
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);
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@ -64,7 +64,7 @@ module ad_addsub (
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input clk;
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input clk;
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input [(A_WIDTH-1):0] A;
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input [(A_WIDTH-1):0] A;
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input [(A_WIDTH-1):0] overflow;
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input [(A_WIDTH-1):0] Amax;
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output [(A_WIDTH-1):0] out;
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output [(A_WIDTH-1):0] out;
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input CE;
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input CE;
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@ -75,8 +75,8 @@ module ad_addsub (
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reg [A_WIDTH:0] out_d2 = 'b0;
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reg [A_WIDTH:0] out_d2 = 'b0;
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reg [(A_WIDTH-1):0] A_d = 'b0;
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reg [(A_WIDTH-1):0] A_d = 'b0;
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reg [(A_WIDTH-1):0] A_d2 = 'b0;
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reg [(A_WIDTH-1):0] A_d2 = 'b0;
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reg [(A_WIDTH-1):0] overflow_d = 'b0;
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reg [(A_WIDTH-1):0] Amax_d = 'b0;
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reg [(A_WIDTH-1):0] overflow_d2 = 'b0;
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reg [(A_WIDTH-1):0] Amax_d2 = 'b0;
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// constant regs
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// constant regs
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@ -87,8 +87,8 @@ module ad_addsub (
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always @(posedge clk) begin
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always @(posedge clk) begin
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A_d <= A;
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A_d <= A;
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A_d2 <= A_d;
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A_d2 <= A_d;
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overflow_d <= overflow;
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Amax_d <= Amax;
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overflow_d2 <= overflow_d;
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Amax_d2 <= Amax_d;
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end
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end
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// ADDER/SUBSTRACTER
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// ADDER/SUBSTRACTER
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@ -101,18 +101,18 @@ module ad_addsub (
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end
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end
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end
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end
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// Resolve overflow
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// Resolve
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always @(posedge clk) begin
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always @(posedge clk) begin
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if ( ADD_SUB == ADDER ) begin
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if ( ADD_SUB == ADDER ) begin
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if ( out_d > overflow_d2 ) begin
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if ( out_d > Amax_d2 ) begin
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out_d2 <= out_d - overflow_d2;
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out_d2 <= out_d - Amax_d2;
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end else begin
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end else begin
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out_d2 <= out_d;
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out_d2 <= out_d;
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end
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end
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end else begin // SUBSTRACTER
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end else begin // SUBSTRACTER
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if ( out_d[A_WIDTH] == 1'b1 ) begin
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if ( out_d[A_WIDTH] == 1'b1 ) begin
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out_d2 <= overflow_d2 + out_d;
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out_d2 <= Amax_d2 + out_d;
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end else begin
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end else begin
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out_d2 <= out_d;
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out_d2 <= out_d;
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end
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end
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@ -50,8 +50,8 @@ module ad_tdd_control(
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tdd_enable,
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tdd_enable,
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tdd_secondary,
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tdd_secondary,
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tdd_txnrx_only_en,
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tdd_tx_only,
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tdd_txnrx_only,
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tdd_rx_only,
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tdd_burst_count,
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tdd_burst_count,
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tdd_counter_init,
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tdd_counter_init,
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tdd_frame_length,
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tdd_frame_length,
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@ -98,8 +98,8 @@ module ad_tdd_control(
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input tdd_enable;
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input tdd_enable;
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input tdd_secondary;
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input tdd_secondary;
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input tdd_txnrx_only_en;
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input tdd_tx_only;
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input tdd_txnrx_only;
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input tdd_rx_only;
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input [ 7:0] tdd_burst_count;
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input [ 7:0] tdd_burst_count;
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input [23:0] tdd_counter_init;
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input [23:0] tdd_counter_init;
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input [23:0] tdd_frame_length;
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input [23:0] tdd_frame_length;
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@ -177,6 +177,8 @@ module ad_tdd_control(
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire tdd_txrx_only_en_s;
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assign tdd_counter_status = tdd_counter;
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assign tdd_counter_status = tdd_counter;
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// ***************************************************************************
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// ***************************************************************************
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@ -208,7 +210,7 @@ module ad_tdd_control(
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if (tdd_counter_state == ON) begin
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if (tdd_counter_state == ON) begin
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if (tdd_counter == tdd_frame_length) begin
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if (tdd_counter == tdd_frame_length) begin
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tdd_counter <= 22'h0;
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tdd_counter <= 22'h0;
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if ( tdd_burst_counter > 1) begin // inside a burst
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if (tdd_burst_counter > 1) begin // inside a burst
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tdd_burst_counter <= tdd_burst_counter - 1;
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tdd_burst_counter <= tdd_burst_counter - 1;
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tdd_counter_state <= ON;
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tdd_counter_state <= ON;
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end
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end
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@ -427,7 +429,7 @@ module ad_tdd_control(
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) i_tx_dp_on_1_comp (
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) i_tx_dp_on_1_comp (
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.clk(clk),
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.clk(clk),
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.A(tdd_tx_dp_on_1),
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.A(tdd_tx_dp_on_1),
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.overflow(tdd_frame_length),
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.Amax(tdd_frame_length),
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.out(tdd_tx_dp_on_1_s),
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.out(tdd_tx_dp_on_1_s),
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.CE(1)
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.CE(1)
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);
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);
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@ -439,7 +441,7 @@ module ad_tdd_control(
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) i_tx_dp_on_2_comp (
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) i_tx_dp_on_2_comp (
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.clk(clk),
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.clk(clk),
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.A(tdd_tx_dp_on_2),
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.A(tdd_tx_dp_on_2),
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.overflow(tdd_frame_length),
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.Amax(tdd_frame_length),
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.out(tdd_tx_dp_on_2_s),
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.out(tdd_tx_dp_on_2_s),
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.CE(1)
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.CE(1)
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);
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);
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@ -451,7 +453,7 @@ module ad_tdd_control(
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) i_tx_dp_off_1_comp (
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) i_tx_dp_off_1_comp (
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.clk(clk),
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.clk(clk),
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.A(tdd_tx_dp_off_1),
|
.A(tdd_tx_dp_off_1),
|
||||||
.overflow(tdd_frame_length),
|
.Amax(tdd_frame_length),
|
||||||
.out(tdd_tx_dp_off_1_s),
|
.out(tdd_tx_dp_off_1_s),
|
||||||
.CE(1)
|
.CE(1)
|
||||||
);
|
);
|
||||||
|
@ -463,17 +465,19 @@ module ad_tdd_control(
|
||||||
) i_tx_dp_off_2_comp (
|
) i_tx_dp_off_2_comp (
|
||||||
.clk(clk),
|
.clk(clk),
|
||||||
.A(tdd_tx_dp_off_2),
|
.A(tdd_tx_dp_off_2),
|
||||||
.overflow(tdd_frame_length),
|
.Amax(tdd_frame_length),
|
||||||
.out(tdd_tx_dp_off_2_s),
|
.out(tdd_tx_dp_off_2_s),
|
||||||
.CE(1)
|
.CE(1)
|
||||||
);
|
);
|
||||||
|
|
||||||
// output logic
|
// output logic
|
||||||
|
|
||||||
|
assign tdd_txrx_only_en_s = tdd_tx_only ^ tdd_rx_only;
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if(tdd_counter_state == ON) begin
|
if(tdd_counter_state == ON) begin
|
||||||
if (tdd_txnrx_only_en) begin
|
if (tdd_txrx_only_en_s) begin
|
||||||
tdd_rx_vco_en <= ~tdd_txnrx_only;
|
tdd_rx_vco_en <= tdd_rx_only;
|
||||||
end
|
end
|
||||||
else if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2) begin
|
else if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2) begin
|
||||||
tdd_rx_vco_en <= 1'b1;
|
tdd_rx_vco_en <= 1'b1;
|
||||||
|
@ -488,8 +492,8 @@ module ad_tdd_control(
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if(tdd_counter_state == ON) begin
|
if(tdd_counter_state == ON) begin
|
||||||
if (tdd_txnrx_only_en) begin
|
if (tdd_txrx_only_en_s) begin
|
||||||
tdd_tx_vco_en <= tdd_txnrx_only;
|
tdd_tx_vco_en <= tdd_tx_only;
|
||||||
end
|
end
|
||||||
else if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2) begin
|
else if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2) begin
|
||||||
tdd_tx_vco_en <= 1'b1;
|
tdd_tx_vco_en <= 1'b1;
|
||||||
|
@ -504,8 +508,8 @@ module ad_tdd_control(
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if(tdd_counter_state == ON) begin
|
if(tdd_counter_state == ON) begin
|
||||||
if (tdd_txnrx_only_en) begin
|
if (tdd_txrx_only_en_s) begin
|
||||||
tdd_rx_rf_en <= ~tdd_txnrx_only;
|
tdd_rx_rf_en <= tdd_rx_only;
|
||||||
end
|
end
|
||||||
else if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2) begin
|
else if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2) begin
|
||||||
tdd_rx_rf_en <= 1'b1;
|
tdd_rx_rf_en <= 1'b1;
|
||||||
|
@ -520,8 +524,8 @@ module ad_tdd_control(
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if(tdd_counter_state == ON) begin
|
if(tdd_counter_state == ON) begin
|
||||||
if (tdd_txnrx_only_en) begin
|
if (tdd_txrx_only_en_s) begin
|
||||||
tdd_tx_rf_en <= tdd_txnrx_only;
|
tdd_tx_rf_en <= tdd_tx_only;
|
||||||
end
|
end
|
||||||
else if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2) begin
|
else if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2) begin
|
||||||
tdd_tx_rf_en <= 1'b1;
|
tdd_tx_rf_en <= 1'b1;
|
||||||
|
@ -536,8 +540,8 @@ module ad_tdd_control(
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if(tdd_counter_state == ON) begin
|
if(tdd_counter_state == ON) begin
|
||||||
if (tdd_txnrx_only_en) begin
|
if (tdd_txrx_only_en_s) begin
|
||||||
tdd_tx_dp_en <= tdd_txnrx_only;
|
tdd_tx_dp_en <= tdd_tx_only;
|
||||||
end
|
end
|
||||||
else if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2) begin
|
else if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2) begin
|
||||||
tdd_tx_dp_en <= 1'b1;
|
tdd_tx_dp_en <= 1'b1;
|
||||||
|
|
|
@ -47,8 +47,8 @@ module up_tdd_cntrl (
|
||||||
|
|
||||||
tdd_enable,
|
tdd_enable,
|
||||||
tdd_secondary,
|
tdd_secondary,
|
||||||
tdd_txnrx_only_en,
|
tdd_rx_only,
|
||||||
tdd_txnrx_only,
|
tdd_tx_only,
|
||||||
tdd_burst_count,
|
tdd_burst_count,
|
||||||
tdd_counter_init,
|
tdd_counter_init,
|
||||||
tdd_frame_length,
|
tdd_frame_length,
|
||||||
|
@ -98,8 +98,8 @@ module up_tdd_cntrl (
|
||||||
|
|
||||||
output tdd_enable;
|
output tdd_enable;
|
||||||
output tdd_secondary;
|
output tdd_secondary;
|
||||||
output tdd_txnrx_only_en;
|
output tdd_rx_only;
|
||||||
output tdd_txnrx_only;
|
output tdd_tx_only;
|
||||||
output [ 7:0] tdd_burst_count;
|
output [ 7:0] tdd_burst_count;
|
||||||
output [23:0] tdd_counter_init;
|
output [23:0] tdd_counter_init;
|
||||||
output [23:0] tdd_frame_length;
|
output [23:0] tdd_frame_length;
|
||||||
|
@ -148,8 +148,8 @@ module up_tdd_cntrl (
|
||||||
|
|
||||||
reg up_tdd_enable = 1'h0;
|
reg up_tdd_enable = 1'h0;
|
||||||
reg up_tdd_secondary = 1'h0;
|
reg up_tdd_secondary = 1'h0;
|
||||||
reg up_tdd_txnrx_only_en = 1'h0;
|
reg up_tdd_rx_only = 1'h0;
|
||||||
reg up_tdd_txnrx_only = 1'h0;
|
reg up_tdd_tx_only = 1'h0;
|
||||||
|
|
||||||
reg [ 7:0] up_tdd_burst_count = 8'h0;
|
reg [ 7:0] up_tdd_burst_count = 8'h0;
|
||||||
reg [23:0] up_tdd_counter_init = 24'h0;
|
reg [23:0] up_tdd_counter_init = 24'h0;
|
||||||
|
@ -197,8 +197,8 @@ module up_tdd_cntrl (
|
||||||
up_scratch <= 32'h0;
|
up_scratch <= 32'h0;
|
||||||
up_tdd_enable <= 1'h0;
|
up_tdd_enable <= 1'h0;
|
||||||
up_tdd_secondary <= 1'h0;
|
up_tdd_secondary <= 1'h0;
|
||||||
up_tdd_txnrx_only_en <= 1'h0;
|
up_tdd_rx_only <= 1'h0;
|
||||||
up_tdd_txnrx_only <= 1'h0;
|
up_tdd_tx_only <= 1'h0;
|
||||||
up_tdd_counter_init <= 24'h0;
|
up_tdd_counter_init <= 24'h0;
|
||||||
up_tdd_frame_length <= 24'h0;
|
up_tdd_frame_length <= 24'h0;
|
||||||
up_tdd_burst_count <= 8'h0;
|
up_tdd_burst_count <= 8'h0;
|
||||||
|
@ -225,8 +225,8 @@ module up_tdd_cntrl (
|
||||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
|
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
|
||||||
up_tdd_enable <= up_wdata[0];
|
up_tdd_enable <= up_wdata[0];
|
||||||
up_tdd_secondary <= up_wdata[1];
|
up_tdd_secondary <= up_wdata[1];
|
||||||
up_tdd_txnrx_only_en <= up_wdata[2];
|
up_tdd_rx_only <= up_wdata[2];
|
||||||
up_tdd_txnrx_only <= up_wdata[3];
|
up_tdd_tx_only <= up_wdata[3];
|
||||||
end
|
end
|
||||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
|
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
|
||||||
up_tdd_burst_count <= up_wdata[7:0];
|
up_tdd_burst_count <= up_wdata[7:0];
|
||||||
|
@ -310,7 +310,7 @@ module up_tdd_cntrl (
|
||||||
up_rack <= up_rreq_s;
|
up_rack <= up_rreq_s;
|
||||||
if (up_rreq_s == 1'b1) begin
|
if (up_rreq_s == 1'b1) begin
|
||||||
case (up_raddr[7:0])
|
case (up_raddr[7:0])
|
||||||
8'h10: up_rdata <= {28'h0, up_tdd_txnrx_only, up_tdd_txnrx_only_en, up_tdd_secondary, up_tdd_enable};
|
8'h10: up_rdata <= {28'h0, up_tdd_tx_only, up_tdd_rx_only, up_tdd_secondary, up_tdd_enable};
|
||||||
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
|
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
|
||||||
8'h12: up_rdata <= {8'h0, up_tdd_counter_init};
|
8'h12: up_rdata <= {8'h0, up_tdd_counter_init};
|
||||||
8'h13: up_rdata <= {8'h0, up_tdd_frame_length};
|
8'h13: up_rdata <= {8'h0, up_tdd_frame_length};
|
||||||
|
@ -348,8 +348,8 @@ module up_tdd_cntrl (
|
||||||
.up_clk(up_clk),
|
.up_clk(up_clk),
|
||||||
.up_data_cntrl({up_tdd_enable,
|
.up_data_cntrl({up_tdd_enable,
|
||||||
up_tdd_secondary,
|
up_tdd_secondary,
|
||||||
up_tdd_txnrx_only_en,
|
up_tdd_rx_only,
|
||||||
up_tdd_txnrx_only,
|
up_tdd_tx_only,
|
||||||
up_tdd_burst_count
|
up_tdd_burst_count
|
||||||
}),
|
}),
|
||||||
.up_xfer_done(up_cntrl_xfer_done),
|
.up_xfer_done(up_cntrl_xfer_done),
|
||||||
|
@ -357,8 +357,8 @@ module up_tdd_cntrl (
|
||||||
.d_clk(clk),
|
.d_clk(clk),
|
||||||
.d_data_cntrl({tdd_enable,
|
.d_data_cntrl({tdd_enable,
|
||||||
tdd_secondary,
|
tdd_secondary,
|
||||||
tdd_txnrx_only_en,
|
tdd_rx_only,
|
||||||
tdd_txnrx_only,
|
tdd_tx_only,
|
||||||
tdd_burst_count
|
tdd_burst_count
|
||||||
}));
|
}));
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue