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ad9361_tdd: Some naming and hierarchical changes

main
Istvan Csomortani 2015-06-04 16:46:28 +03:00
parent 47469ad375
commit 2e877389b2
5 changed files with 96 additions and 64 deletions
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17
library/axi_ad9361/axi_ad9361.v
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@ -313,8 +313,6 @@ module axi_ad9361 (
wire dac_valid_i1_s;
wire dac_valid_q1_s;
wire tdd_mode_enable_s;
// signal name changes
assign up_clk = s_axi_aclk;
@ -394,13 +392,20 @@ module axi_ad9361 (
axi_ad9361_tdd i_tdd(
.clk(clk),
.rst(rst),
.tdd_enable(tdd_mode_enable_s),
.tdd_tx_dp_en(tdd_tx_dp_en_s),
.tdd_rx_vco_en(tdd_rx_vco_en_s),
.tdd_tx_vco_en(tdd_tx_vco_en_s),
.tdd_rx_rf_en(tdd_rx_rf_en_s),
.tdd_tx_rf_en(tdd_tx_rf_en_s),
.tdd_status(tdd_status_s),
.tx_valid_i0(dac_valid_i0_s),
.tx_valid_q0(dac_valid_q0_s),
.tx_valid_i1(dac_valid_i1_s),
.tx_valid_q1(dac_valid_q1_s),
.tdd_tx_valid_i0(dac_valid_i0),
.tdd_tx_valid_q0(dac_valid_q0),
.tdd_tx_valid_i1(dac_valid_i1),
.tdd_tx_valid_q1(dac_valid_q1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq_s),
@ -414,6 +419,7 @@ module axi_ad9361 (
.tdd_dbg(tdd_dbg)
);
// receive
axi_ad9361_rx #(
@ -507,11 +513,6 @@ module axi_ad9361 (
.up_rdata (up_rdata_tx_s),
.up_rack (up_rack_tx_s));
assign dac_valid_i0 = (tdd_mode_enable_s == 1) ? (dac_valid_i0_s & tdd_tx_dp_en_s) : dac_valid_i0_s;
assign dac_valid_q0 = (tdd_mode_enable_s == 1) ? (dac_valid_q0_s & tdd_tx_dp_en_s) : dac_valid_q0_s;
assign dac_valid_i1 = (tdd_mode_enable_s == 1) ? (dac_valid_i1_s & tdd_tx_dp_en_s) : dac_valid_i1_s;
assign dac_valid_q1 = (tdd_mode_enable_s == 1) ? (dac_valid_q1_s & tdd_tx_dp_en_s) : dac_valid_q1_s;
// axi interface
up_axi i_up_axi (

47
library/axi_ad9361/axi_ad9361_tdd.v
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@ -48,7 +48,6 @@ module axi_ad9361_tdd (
// control signals from the tdd control
tdd_enable,
tdd_tx_dp_en,
tdd_rx_vco_en,
tdd_tx_vco_en,
@ -59,6 +58,18 @@ module axi_ad9361_tdd (
tdd_status,
// tx data flow control
tx_valid_i0,
tx_valid_q0,
tx_valid_i1,
tx_valid_q1,
tdd_tx_valid_i0,
tdd_tx_valid_q0,
tdd_tx_valid_i1,
tdd_tx_valid_q1,
// bus interface
up_rstn,
@ -80,7 +91,6 @@ module axi_ad9361_tdd (
// control signals from the tdd control
output tdd_enable;
output tdd_tx_dp_en;
output tdd_rx_vco_en;
output tdd_tx_vco_en;
@ -89,6 +99,18 @@ module axi_ad9361_tdd (
input [ 7:0] tdd_status;
// tx data flow control
input tx_valid_i0;
input tx_valid_q0;
input tx_valid_i1;
input tx_valid_q1;
output tdd_tx_valid_i0;
output tdd_tx_valid_q0;
output tdd_tx_valid_i1;
output tdd_tx_valid_q1;
// bus interface
input up_rstn;
@ -110,8 +132,8 @@ module axi_ad9361_tdd (
wire tdd_enable_s;
wire tdd_secondary_s;
wire [ 7:0] tdd_burst_count_s;
wire tdd_txnrx_only_en_s;
wire tdd_txnrx_only_s;
wire tdd_rx_only_s;
wire tdd_tx_only_s;
wire [23:0] tdd_counter_init_s;
wire [23:0] tdd_frame_length_s;
wire [23:0] tdd_vco_rx_on_1_s;
@ -137,10 +159,15 @@ module axi_ad9361_tdd (
wire [23:0] tdd_counter_status;
assign tdd_dbg = {tdd_counter_status, tdd_enable, tdd_tx_dp_en,
assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_tx_dp_en,
tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
assign tdd_enable = tdd_enable_s;
// tx data flow control
assign tdd_tx_valid_i0 = tx_valid_i0 & tdd_enable_s;
assign tdd_tx_valid_q0 = tx_valid_q0 & tdd_enable_s;
assign tdd_tx_valid_i1 = tx_valid_i1 & tdd_enable_s;
assign tdd_tx_valid_q1 = tx_valid_q1 & tdd_enable_s;
// instantiations
@ -150,8 +177,8 @@ module axi_ad9361_tdd (
.tdd_enable(tdd_enable_s),
.tdd_secondary(tdd_secondary_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_txnrx_only_en(tdd_txnrx_only_en_s),
.tdd_txnrx_only(tdd_txnrx_only_s),
.tdd_tx_only(tdd_tx_only_s),
.tdd_rx_only(tdd_rx_only_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
@ -194,8 +221,8 @@ module axi_ad9361_tdd (
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_txnrx_only_en(tdd_txnrx_only_en_s),
.tdd_txnrx_only(tdd_txnrx_only_s),
.tdd_rx_only(tdd_rx_only_s),
.tdd_tx_only(tdd_tx_only_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),

24
library/common/ad_addsub.v
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@ -37,8 +37,8 @@
// ***************************************************************************
// ***************************************************************************
// A simple adder/substracter width preconfigured input ports width and overflow value
// Output = A - B or A + B
// A simple adder/substracter width preconfigured input ports width and turn-around value
// Output = A - B_constant or A + B_constant
// Constraints: Awidth >= Bwidth
`timescale 1ns/1ps
@ -46,7 +46,7 @@
module ad_addsub (
clk,
A,
overflow,
Amax,
out,
CE
);
@ -64,7 +64,7 @@ module ad_addsub (
input clk;
input [(A_WIDTH-1):0] A;
input [(A_WIDTH-1):0] overflow;
input [(A_WIDTH-1):0] Amax;
output [(A_WIDTH-1):0] out;
input CE;
@ -75,8 +75,8 @@ module ad_addsub (
reg [A_WIDTH:0] out_d2 = 'b0;
reg [(A_WIDTH-1):0] A_d = 'b0;
reg [(A_WIDTH-1):0] A_d2 = 'b0;
reg [(A_WIDTH-1):0] overflow_d = 'b0;
reg [(A_WIDTH-1):0] overflow_d2 = 'b0;
reg [(A_WIDTH-1):0] Amax_d = 'b0;
reg [(A_WIDTH-1):0] Amax_d2 = 'b0;
// constant regs
@ -87,8 +87,8 @@ module ad_addsub (
always @(posedge clk) begin
A_d <= A;
A_d2 <= A_d;
overflow_d <= overflow;
overflow_d2 <= overflow_d;
Amax_d <= Amax;
Amax_d2 <= Amax_d;
end
// ADDER/SUBSTRACTER
@ -101,18 +101,18 @@ module ad_addsub (
end
end
// Resolve overflow
// Resolve
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
if ( out_d > overflow_d2 ) begin
out_d2 <= out_d - overflow_d2;
if ( out_d > Amax_d2 ) begin
out_d2 <= out_d - Amax_d2;
end else begin
out_d2 <= out_d;
end
end else begin // SUBSTRACTER
if ( out_d[A_WIDTH] == 1'b1 ) begin
out_d2 <= overflow_d2 + out_d;
out_d2 <= Amax_d2 + out_d;
end else begin
out_d2 <= out_d;
end

40
library/common/ad_tdd_control.v
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@ -50,8 +50,8 @@ module ad_tdd_control(
tdd_enable,
tdd_secondary,
tdd_txnrx_only_en,
tdd_txnrx_only,
tdd_tx_only,
tdd_rx_only,
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
@ -98,8 +98,8 @@ module ad_tdd_control(
input tdd_enable;
input tdd_secondary;
input tdd_txnrx_only_en;
input tdd_txnrx_only;
input tdd_tx_only;
input tdd_rx_only;
input [ 7:0] tdd_burst_count;
input [23:0] tdd_counter_init;
input [23:0] tdd_frame_length;
@ -177,6 +177,8 @@ module ad_tdd_control(
wire [23:0] tdd_tx_dp_off_1_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire tdd_txrx_only_en_s;
assign tdd_counter_status = tdd_counter;
// ***************************************************************************
@ -427,7 +429,7 @@ module ad_tdd_control(
) i_tx_dp_on_1_comp (
.clk(clk),
.A(tdd_tx_dp_on_1),
.overflow(tdd_frame_length),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_on_1_s),
.CE(1)
);
@ -439,7 +441,7 @@ module ad_tdd_control(
) i_tx_dp_on_2_comp (
.clk(clk),
.A(tdd_tx_dp_on_2),
.overflow(tdd_frame_length),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_on_2_s),
.CE(1)
);
@ -451,7 +453,7 @@ module ad_tdd_control(
) i_tx_dp_off_1_comp (
.clk(clk),
.A(tdd_tx_dp_off_1),
.overflow(tdd_frame_length),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_off_1_s),
.CE(1)
);
@ -463,17 +465,19 @@ module ad_tdd_control(
) i_tx_dp_off_2_comp (
.clk(clk),
.A(tdd_tx_dp_off_2),
.overflow(tdd_frame_length),
.Amax(tdd_frame_length),
.out(tdd_tx_dp_off_2_s),
.CE(1)
);
// output logic
assign tdd_txrx_only_en_s = tdd_tx_only ^ tdd_rx_only;
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_txnrx_only_en) begin
tdd_rx_vco_en <= ~tdd_txnrx_only;
if (tdd_txrx_only_en_s) begin
tdd_rx_vco_en <= tdd_rx_only;
end
else if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2) begin
tdd_rx_vco_en <= 1'b1;
@ -488,8 +492,8 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_txnrx_only_en) begin
tdd_tx_vco_en <= tdd_txnrx_only;
if (tdd_txrx_only_en_s) begin
tdd_tx_vco_en <= tdd_tx_only;
end
else if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2) begin
tdd_tx_vco_en <= 1'b1;
@ -504,8 +508,8 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_txnrx_only_en) begin
tdd_rx_rf_en <= ~tdd_txnrx_only;
if (tdd_txrx_only_en_s) begin
tdd_rx_rf_en <= tdd_rx_only;
end
else if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2) begin
tdd_rx_rf_en <= 1'b1;
@ -520,8 +524,8 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_txnrx_only_en) begin
tdd_tx_rf_en <= tdd_txnrx_only;
if (tdd_txrx_only_en_s) begin
tdd_tx_rf_en <= tdd_tx_only;
end
else if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2) begin
tdd_tx_rf_en <= 1'b1;
@ -536,8 +540,8 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_txnrx_only_en) begin
tdd_tx_dp_en <= tdd_txnrx_only;
if (tdd_txrx_only_en_s) begin
tdd_tx_dp_en <= tdd_tx_only;
end
else if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2) begin
tdd_tx_dp_en <= 1'b1;

30
library/common/up_tdd_cntrl.v
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@ -47,8 +47,8 @@ module up_tdd_cntrl (
tdd_enable,
tdd_secondary,
tdd_txnrx_only_en,
tdd_txnrx_only,
tdd_rx_only,
tdd_tx_only,
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
@ -98,8 +98,8 @@ module up_tdd_cntrl (
output tdd_enable;
output tdd_secondary;
output tdd_txnrx_only_en;
output tdd_txnrx_only;
output tdd_rx_only;
output tdd_tx_only;
output [ 7:0] tdd_burst_count;
output [23:0] tdd_counter_init;
output [23:0] tdd_frame_length;
@ -148,8 +148,8 @@ module up_tdd_cntrl (
reg up_tdd_enable = 1'h0;
reg up_tdd_secondary = 1'h0;
reg up_tdd_txnrx_only_en = 1'h0;
reg up_tdd_txnrx_only = 1'h0;
reg up_tdd_rx_only = 1'h0;
reg up_tdd_tx_only = 1'h0;
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
@ -197,8 +197,8 @@ module up_tdd_cntrl (
up_scratch <= 32'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
up_tdd_txnrx_only_en <= 1'h0;
up_tdd_txnrx_only <= 1'h0;
up_tdd_rx_only <= 1'h0;
up_tdd_tx_only <= 1'h0;
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
@ -225,8 +225,8 @@ module up_tdd_cntrl (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_tdd_enable <= up_wdata[0];
up_tdd_secondary <= up_wdata[1];
up_tdd_txnrx_only_en <= up_wdata[2];
up_tdd_txnrx_only <= up_wdata[3];
up_tdd_rx_only <= up_wdata[2];
up_tdd_tx_only <= up_wdata[3];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_burst_count <= up_wdata[7:0];
@ -310,7 +310,7 @@ module up_tdd_cntrl (
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h10: up_rdata <= {28'h0, up_tdd_txnrx_only, up_tdd_txnrx_only_en, up_tdd_secondary, up_tdd_enable};
8'h10: up_rdata <= {28'h0, up_tdd_tx_only, up_tdd_rx_only, up_tdd_secondary, up_tdd_enable};
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
8'h12: up_rdata <= {8'h0, up_tdd_counter_init};
8'h13: up_rdata <= {8'h0, up_tdd_frame_length};
@ -348,8 +348,8 @@ module up_tdd_cntrl (
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_secondary,
up_tdd_txnrx_only_en,
up_tdd_txnrx_only,
up_tdd_rx_only,
up_tdd_tx_only,
up_tdd_burst_count
}),
.up_xfer_done(up_cntrl_xfer_done),
@ -357,8 +357,8 @@ module up_tdd_cntrl (
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_secondary,
tdd_txnrx_only_en,
tdd_txnrx_only,
tdd_rx_only,
tdd_tx_only,
tdd_burst_count
}));