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daq2: Provide DAC lane map 

Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-05-29 13:36:27 +02:00
parent 4bf5990451
commit 2e8be3d7a6
1 changed files with 1 additions and 1 deletions
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2
projects/daq2/common/daq2_bd.tcl
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@ -78,7 +78,7 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
# connections (dac)
ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd
ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1}
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
ad_connect axi_ad9144_jesd/tx_data_tdata axi_ad9144_core/tx_data
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk