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m2k: Replace logic analyzer MMCM 

The MMCM generating the logic analyzer clock unfortunately consumes a
disproportionately large amount of power compared to the rest of the
design.

Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs.
The IO PLL is running anyway so the power requirement is much lower.

For the time being this means we loose the ability to source the clock from
an external pin. But that feature is not supported by software at the
moment anyway. We'll bring it eventually when required.

This changes reduces power consumption by roughly 100mW.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-03-23 14:56:35 +01:00
parent e616c8da0b
commit 2eaf931e07
3 changed files with 13 additions and 30 deletions
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30
projects/m2k/common/m2k_bd.tcl
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@ -14,15 +14,12 @@ create_bd_port -dir I tx_clk
create_bd_port -dir O txiq create_bd_port -dir O txiq
create_bd_port -dir O -from 11 -to 0 txd create_bd_port -dir O -from 11 -to 0 txd
set clk_generator [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 clk_generator] # Logic analyzer (FCLK2): 100 MHz
set_property -dict [list CONFIG.VCO_DIV {1}] $clk_generator
set_property -dict [list CONFIG.VCO_MUL {8}] $clk_generator set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.CLK0_DIV {10}] $clk_generator set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
set_property -dict [list CONFIG.CLK1_DIV {5}] $clk_generator
set_property -dict [list CONFIG.CLK0_PHASE {180}] $clk_generator ad_connect logic_analyzer_clk sys_ps7/FCLK_CLK2
set_property -dict [list CONFIG.CLK1_PHASE {180}] $clk_generator
set_property -dict [list CONFIG.CLKIN_PERIOD {10}] $clk_generator
set_property -dict [list CONFIG.CLKIN2_PERIOD {12.5}] $clk_generator
set logic_analyzer [create_bd_cell -type ip -vlnv analog.com:user:axi_logic_analyzer:1.0 logic_analyzer] set logic_analyzer [create_bd_cell -type ip -vlnv analog.com:user:axi_logic_analyzer:1.0 logic_analyzer]
@ -98,16 +95,13 @@ ad_connect trigger_i logic_analyzer/trigger_i
ad_connect data_o logic_analyzer/data_o ad_connect data_o logic_analyzer/data_o
ad_connect data_t logic_analyzer/data_t ad_connect data_t logic_analyzer/data_t
ad_connect sys_cpu_clk clk_generator/clk ad_connect logic_analyzer_clk logic_analyzer/clk
ad_connect logic_analyzer/clk clk_generator/clk_0 ad_connect logic_analyzer_clk pattern_generator_dmac/fifo_rd_clk
ad_connect logic_analyzer/clk_out clk_generator/clk2
ad_connect pattern_generator_dmac/fifo_rd_clk clk_generator/clk_0 ad_connect logic_analyzer_clk la_trigger_fifo/clk
ad_connect logic_analyzer_clk logic_analyzer_dmac/fifo_wr_clk
ad_connect clk_generator/clk_0 la_trigger_fifo/clk ad_connect logic_analyzer_clk logic_analyzer_reset/slowest_sync_clk
ad_connect logic_analyzer_dmac/fifo_wr_clk clk_generator/clk_0
ad_connect logic_analyzer_reset/slowest_sync_clk clk_generator/clk_0
ad_connect logic_analyzer_reset/ext_reset_in sys_rstgen/peripheral_aresetn ad_connect logic_analyzer_reset/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect logic_analyzer_reset/bus_struct_reset la_trigger_fifo/rst ad_connect logic_analyzer_reset/bus_struct_reset la_trigger_fifo/rst
@ -209,7 +203,7 @@ ad_connect axi_ad9963/dac_dunf ad9963_dac_dmac_a/fifo_rd_underflow
# interconnects # interconnects
ad_cpu_interconnect 0x70000000 clk_generator #ad_cpu_interconnect 0x70000000 clk_generator
ad_cpu_interconnect 0x70100000 logic_analyzer ad_cpu_interconnect 0x70100000 logic_analyzer
ad_cpu_interconnect 0x70200000 axi_ad9963 ad_cpu_interconnect 0x70200000 axi_ad9963
ad_cpu_interconnect 0x7C400000 logic_analyzer_dmac ad_cpu_interconnect 0x7C400000 logic_analyzer_dmac

7
projects/m2k/standalone/system_constr.xdc
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@ -69,12 +69,7 @@ create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}]
create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"]
create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"]
create_clock -name clk_fpga_2 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]"]
set_clock_groups -name exclusive_ -physically_exclusive \
-group [get_clocks mmcm_clk_0_s_1] -group [get_clocks mmcm_clk_0_s_2] -group [get_clocks mmcm_clk_0_s]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {i_system_wrapper/system_i/logic_analyzer/inst/i_registers/i_xfer_cntrl/Q[95]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets trigger_bd_IOBUF[0]_inst/O]
set_false_path -from [get_clocks data_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/data_m1_reg[0]/D}] set_false_path -from [get_clocks data_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/data_m1_reg[0]/D}]
set_false_path -from [get_clocks trigger_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/trigger_m1_reg[0]/D}] set_false_path -from [get_clocks trigger_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/trigger_m1_reg[0]/D}]

6
projects/m2k/zed/system_constr.xdc
View File

@ -64,9 +64,3 @@ create_clock -name tx_clk -period 6.66 [get_ports tx_clk]
create_clock -name trigger_clk -period 12.5 [get_ports trigger_bd[0]] create_clock -name trigger_clk -period 12.5 [get_ports trigger_bd[0]]
create_clock -name data_clk -period 12.5 [get_ports data_bd[0]] create_clock -name data_clk -period 12.5 [get_ports data_bd[0]]
set_clock_groups -name exclusive_ -physically_exclusive \
-group [get_clocks mmcm_clk_0_s_1] -group [get_clocks mmcm_clk_0_s_2] -group [get_clocks mmcm_clk_0_s_3]
set_false_path -from [get_clocks data_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/data_m1_reg[0]/D}]
set_false_path -from [get_clocks trigger_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/trigger_m1_reg[0]/D}]