zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym

main
Istvan Csomortani 2018-08-14 12:24:01 +01:00 committed by István Csomortáni
parent 1e074726db
commit 2f0dbe6151
10 changed files with 80 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
library/Makefile
View File

@ -64,7 +64,7 @@ clean:
$(MAKE) -C intel/avl_adxphy clean $(MAKE) -C intel/avl_adxphy clean
$(MAKE) -C intel/avl_dacfifo clean $(MAKE) -C intel/avl_dacfifo clean
$(MAKE) -C intel/axi_adxcvr clean $(MAKE) -C intel/axi_adxcvr clean
$(MAKE) -C intel/common/alt_mem_asym clean $(MAKE) -C intel/common/intel_mem_asym clean
$(MAKE) -C intel/common/intel_serdes clean $(MAKE) -C intel/common/intel_serdes clean
$(MAKE) -C intel/jesd204_phy clean $(MAKE) -C intel/jesd204_phy clean
$(MAKE) -C intel/util_clkdiv clean $(MAKE) -C intel/util_clkdiv clean
@ -174,7 +174,7 @@ lib:
$(MAKE) -C intel/avl_adxphy $(MAKE) -C intel/avl_adxphy
$(MAKE) -C intel/avl_dacfifo $(MAKE) -C intel/avl_dacfifo
$(MAKE) -C intel/axi_adxcvr $(MAKE) -C intel/axi_adxcvr
$(MAKE) -C intel/common/alt_mem_asym $(MAKE) -C intel/common/intel_mem_asym
$(MAKE) -C intel/common/intel_serdes $(MAKE) -C intel/common/intel_serdes
$(MAKE) -C intel/jesd204_phy $(MAKE) -C intel/jesd204_phy
$(MAKE) -C intel/util_clkdiv $(MAKE) -C intel/util_clkdiv

34
library/intel/avl_dacfifo/avl_dacfifo_hw.tcl
View File

@ -111,29 +111,29 @@ proc p_avl_dacfifo_elab {} {
# intel memory for WRITE side # intel memory for WRITE side
add_hdl_instance alt_mem_asym_wr alt_mem_asym add_hdl_instance ad_mem_asym_wr intel_mem_asym
set_instance_parameter_value alt_mem_asym_wr DEVICE_FAMILY $m_device_family set_instance_parameter_value ad_mem_asym_wr DEVICE_FAMILY $m_device_family
set_instance_parameter_value alt_mem_asym_wr A_ADDRESS_WIDTH $m_dma_mem_addr_width set_instance_parameter_value ad_mem_asym_wr A_ADDRESS_WIDTH $m_dma_mem_addr_width
set_instance_parameter_value alt_mem_asym_wr A_DATA_WIDTH $m_dma_data_width set_instance_parameter_value ad_mem_asym_wr A_DATA_WIDTH $m_dma_data_width
set_instance_parameter_value alt_mem_asym_wr B_DATA_WIDTH $m_avl_data_width set_instance_parameter_value ad_mem_asym_wr B_DATA_WIDTH $m_avl_data_width
# intel memory for READ side # intel memory for READ side
add_hdl_instance alt_mem_asym_rd alt_mem_asym add_hdl_instance ad_mem_asym_rd intel_mem_asym
set_instance_parameter_value alt_mem_asym_rd DEVICE_FAMILY $m_device_family set_instance_parameter_value ad_mem_asym_rd DEVICE_FAMILY $m_device_family
set_instance_parameter_value alt_mem_asym_rd A_ADDRESS_WIDTH 0 set_instance_parameter_value ad_mem_asym_rd A_ADDRESS_WIDTH 0
set_instance_parameter_value alt_mem_asym_rd A_DATA_WIDTH $m_avl_data_width set_instance_parameter_value ad_mem_asym_rd A_DATA_WIDTH $m_avl_data_width
set_instance_parameter_value alt_mem_asym_rd B_ADDRESS_WIDTH $m_dac_mem_addr_width set_instance_parameter_value ad_mem_asym_rd B_ADDRESS_WIDTH $m_dac_mem_addr_width
set_instance_parameter_value alt_mem_asym_rd B_DATA_WIDTH $m_dac_data_width set_instance_parameter_value ad_mem_asym_rd B_DATA_WIDTH $m_dac_data_width
# intel memory for bypass logic # intel memory for bypass logic
add_hdl_instance alt_mem_asym_bypass alt_mem_asym add_hdl_instance ad_mem_asym_bypass intel_mem_asym
set_instance_parameter_value alt_mem_asym_bypass DEVICE_FAMILY $m_device_family set_instance_parameter_value ad_mem_asym_bypass DEVICE_FAMILY $m_device_family
set_instance_parameter_value alt_mem_asym_bypass A_ADDRESS_WIDTH $m_dma_mem_addr_width_bypass set_instance_parameter_value ad_mem_asym_bypass A_ADDRESS_WIDTH $m_dma_mem_addr_width_bypass
set_instance_parameter_value alt_mem_asym_bypass A_DATA_WIDTH $m_dma_data_width set_instance_parameter_value ad_mem_asym_bypass A_DATA_WIDTH $m_dma_data_width
set_instance_parameter_value alt_mem_asym_bypass B_ADDRESS_WIDTH $m_dac_mem_addr_width_bypass set_instance_parameter_value ad_mem_asym_bypass B_ADDRESS_WIDTH $m_dac_mem_addr_width_bypass
set_instance_parameter_value alt_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width set_instance_parameter_value ad_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width
} }

2
library/intel/avl_dacfifo/avl_dacfifo_rd.v
View File

@ -158,7 +158,7 @@ module avl_dacfifo_rd #(
// An asymmetric memory to transfer data from Avalon interface to DAC // An asymmetric memory to transfer data from Avalon interface to DAC
// interface // interface
alt_mem_asym_rd i_mem_asym ( ad_mem_asym_rd i_mem_asym (
.mem_i_wrclock (avl_clk), .mem_i_wrclock (avl_clk),
.mem_i_wren (avl_readdatavalid), .mem_i_wren (avl_readdatavalid),
.mem_i_wraddress (avl_mem_waddr), .mem_i_wraddress (avl_mem_waddr),

2
library/intel/avl_dacfifo/avl_dacfifo_wr.v
View File

@ -147,7 +147,7 @@ module avl_dacfifo_wr #(
// An asymmetric memory to transfer data from DMAC interface to Avalon Memory Map // An asymmetric memory to transfer data from DMAC interface to Avalon Memory Map
// interface // interface
alt_mem_asym_wr i_mem_asym ( ad_mem_asym_wr i_mem_asym (
.mem_i_wrclock (dma_clk), .mem_i_wrclock (dma_clk),
.mem_i_wren (dma_mem_wea_s), .mem_i_wren (dma_mem_wea_s),
.mem_i_wraddress (dma_mem_waddr), .mem_i_wraddress (dma_mem_waddr),

2
library/intel/avl_dacfifo/util_dacfifo_bypass.v
View File

@ -109,7 +109,7 @@ module util_dacfifo_bypass #(
// An asymmetric memory to transfer data from DMAC interface to DAC interface // An asymmetric memory to transfer data from DMAC interface to DAC interface
alt_mem_asym_bypass i_mem_asym ( ad_mem_asym_bypass i_mem_asym (
.mem_i_wrclock (dma_clk), .mem_i_wrclock (dma_clk),
.mem_i_wren (dma_mem_wea_s), .mem_i_wren (dma_mem_wea_s),
.mem_i_wraddress (dma_mem_waddr), .mem_i_wraddress (dma_mem_waddr),

49
library/intel/common/alt_mem_asym/alt_mem_asym_hw.tcl
View File

@ -1,49 +0,0 @@
package require qsys
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create alt_mem_asym {Altera Asymmetric Memory}
set_module_property COMPOSITION_CALLBACK p_alt_mem_asym
# parameters
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter A_ADDRESS_WIDTH INTEGER 8
ad_ip_parameter A_DATA_WIDTH INTEGER 512
ad_ip_parameter B_ADDRESS_WIDTH INTEGER 8
ad_ip_parameter B_DATA_WIDTH INTEGER 64
# compose
proc p_alt_mem_asym {} {
set m_addr_width_a [get_parameter_value "A_ADDRESS_WIDTH"]
set m_data_width_a [get_parameter_value "A_DATA_WIDTH"]
set m_addr_width_b [get_parameter_value "B_ADDRESS_WIDTH"]
set m_data_width_b [get_parameter_value "B_DATA_WIDTH"]
set m_size [expr ((2**$m_addr_width_a)*$m_data_width_a)]
if {$m_addr_width_a == 0} {
set m_size [expr ((2**$m_addr_width_b)*$m_data_width_b)]
}
add_instance alt_mem ram_2port
set_instance_parameter_value alt_mem {GUI_MODE} 0
set_instance_parameter_value alt_mem {GUI_MEM_IN_BITS} 1
set_instance_parameter_value alt_mem {GUI_MEMSIZE_BITS} $m_size
set_instance_parameter_value alt_mem {GUI_VAR_WIDTH} 1
set_instance_parameter_value alt_mem {GUI_QA_WIDTH} $m_data_width_a
set_instance_parameter_value alt_mem {GUI_DATAA_WIDTH} $m_data_width_a
set_instance_parameter_value alt_mem {GUI_QB_WIDTH} $m_data_width_b
set_instance_parameter_value alt_mem {GUI_READ_OUTPUT_QB} {false}
set_instance_parameter_value alt_mem {GUI_RAM_BLOCK_TYPE} {M20K}
set_instance_parameter_value alt_mem {GUI_CLOCK_TYPE} 1
add_interface mem_i conduit end
add_interface mem_o conduit end
set_interface_property mem_i EXPORT_OF alt_mem.ram_input
set_interface_property mem_o EXPORT_OF alt_mem.ram_output
}

4
library/intel/common/alt_mem_asym/Makefile → library/intel/common/intel_mem_asym/Makefile
View File

@ -3,8 +3,8 @@
## Auto-generated, do not modify! ## Auto-generated, do not modify!
#################################################################################### ####################################################################################
LIBRARY_NAME := alt_mem_asym LIBRARY_NAME := intel_mem_asym
INTEL_DEPS += alt_mem_asym_hw.tcl INTEL_DEPS += intel_mem_asym_hw.tcl
include ../../../scripts/library.mk include ../../../scripts/library.mk

49
library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl Normal file
View File

@ -0,0 +1,49 @@
package require qsys
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create intel_mem_asym {Intel Asymmetric Memory}
set_module_property COMPOSITION_CALLBACK p_intel_mem_asym
# parameters
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter A_ADDRESS_WIDTH INTEGER 8
ad_ip_parameter A_DATA_WIDTH INTEGER 512
ad_ip_parameter B_ADDRESS_WIDTH INTEGER 8
ad_ip_parameter B_DATA_WIDTH INTEGER 64
# compose
proc p_intel_mem_asym {} {
set m_addr_width_a [get_parameter_value "A_ADDRESS_WIDTH"]
set m_data_width_a [get_parameter_value "A_DATA_WIDTH"]
set m_addr_width_b [get_parameter_value "B_ADDRESS_WIDTH"]
set m_data_width_b [get_parameter_value "B_DATA_WIDTH"]
set m_size [expr ((2**$m_addr_width_a)*$m_data_width_a)]
if {$m_addr_width_a == 0} {
set m_size [expr ((2**$m_addr_width_b)*$m_data_width_b)]
}
add_instance intel_mem ram_2port
set_instance_parameter_value intel_mem {GUI_MODE} 0
set_instance_parameter_value intel_mem {GUI_MEM_IN_BITS} 1
set_instance_parameter_value intel_mem {GUI_MEMSIZE_BITS} $m_size
set_instance_parameter_value intel_mem {GUI_VAR_WIDTH} 1
set_instance_parameter_value intel_mem {GUI_QA_WIDTH} $m_data_width_a
set_instance_parameter_value intel_mem {GUI_DATAA_WIDTH} $m_data_width_a
set_instance_parameter_value intel_mem {GUI_QB_WIDTH} $m_data_width_b
set_instance_parameter_value intel_mem {GUI_READ_OUTPUT_QB} {false}
set_instance_parameter_value intel_mem {GUI_RAM_BLOCK_TYPE} {M20K}
set_instance_parameter_value intel_mem {GUI_CLOCK_TYPE} 1
add_interface mem_i conduit end
add_interface mem_o conduit end
set_interface_property mem_i EXPORT_OF intel_mem.ram_input
set_interface_property mem_o EXPORT_OF intel_mem.ram_output
}

2
library/util_adcfifo/util_adcfifo.v
View File

@ -210,7 +210,7 @@ module util_adcfifo #(
generate generate
if (FPGA_TECHNOLOGY == 1) begin if (FPGA_TECHNOLOGY == 1) begin
alt_mem_asym i_mem_asym ( mem_asym i_mem_asym (
.mem_i_wrclock (adc_clk), .mem_i_wrclock (adc_clk),
.mem_i_wren (adc_wr_int), .mem_i_wren (adc_wr_int),
.mem_i_wraddress (adc_waddr_int), .mem_i_wraddress (adc_waddr_int),

12
library/util_adcfifo/util_adcfifo_hw.tcl
View File

@ -37,12 +37,12 @@ proc p_util_adcfifo {} {
# intel memory # intel memory
add_hdl_instance alt_mem_asym alt_mem_asym add_hdl_instance mem_asym intel_mem_asym
set_instance_parameter_value alt_mem_asym DEVICE_FAMILY $m_device_family set_instance_parameter_value mem_asym DEVICE_FAMILY $m_device_family
set_instance_parameter_value alt_mem_asym A_ADDRESS_WIDTH 0 set_instance_parameter_value mem_asym A_ADDRESS_WIDTH 0
set_instance_parameter_value alt_mem_asym A_DATA_WIDTH $m_adc_data_width set_instance_parameter_value mem_asym A_DATA_WIDTH $m_adc_data_width
set_instance_parameter_value alt_mem_asym B_ADDRESS_WIDTH $m_dma_addr_width set_instance_parameter_value mem_asym B_ADDRESS_WIDTH $m_dma_addr_width
set_instance_parameter_value alt_mem_asym B_DATA_WIDTH $m_dma_data_width set_instance_parameter_value mem_asym B_DATA_WIDTH $m_dma_data_width
# interfaces # interfaces